|
We're trying to get a C6205 based PCI card running. I have the
following questions/problems: 1. Must the C6205 reset be a high-low-high pulse, even if you are not using the PLL?. 2. What relationship must the DSP reset and PCI reset have?. Since the PCI EEPROM read only takes place after the DSP has been released from reset, I assume the DSP has to be taken out of reset before the PCI reset is de-asserted or a very short time after in order for the PCI configuration to be setup from the EEPROM. I currently have the PCI reset tied to the DSP reset, through a Schmitt trigger buffer and am not using the PLL. This means that the DSP reset starts off low and goes high, when the PCI reset is deasserted. From the PC side I am able to verify that the PCI configuration data was read from the EEPROM OK (i.e I can read my vendor/device id). However I'm unable to access the DSP reliably from CCS via JTAG even if the DSP is set in "start running code from internal memory at location 0x0" boot mode. ------------------------ Stephen Turner AudioScience, Inc. |
C6205: PCI and DSP reset questions/problems
Started by ●June 12, 2003
