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Hi everybody,
I've got a problem with the DSP board we just designed, I hope you can
help me on this one:
The design is mainly based on the 6711DSK, same DSP (6711 150MHz),
same SDRAM family (MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK)
clock at 100MHz through the EMIF, CE0 is used.
My board works well, except for the SDRAMs. I am able to fill entirely my
SDRAM with data using Edit->Memory->Fill in CCS. Then i am able to read it by
using File->Data->Save in CCS
still. So far it's fine.
Problem starts to occur when i want to load my program into SDRAM (my DSP
internal mem is a 4-way cache), this error occur : "Data Verification Fail
at address 0x80000150. Please verify target memory and memory map"
I've been trying to debug this problem by optimizing the EMIF settings
for SDRAM (SDCTL, SDTIM, SDEXT) but i have been unsuccessfull so far.
I begin to question the hardware design. But it's should be OK as the
SDRAMs are directly connected to my DSP, it's quite a straightforward
design, and as i said based on the 6711DSK.
Any suggestions to help me pointing the problem would be welcome,
Thanks,
Ludo ------------------------- Ludovic Tramart, DSP System Engineer www.fulcrumvoicetech.com FULCRUM, Hillbottom Road High Wycombe, HP12 4HJ Tel : +44 (0)1494 437575 Fax: +44 (0)1494 473324 |
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problem with SDRAM
Started by ●June 23, 2003
Reply by ●June 23, 20032003-06-23
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Ludovic Tramart- You have to separate whether it's hardware or software to start debugging. Try with SDRAM clock of 50 MHz. Still see the same results? Jeff Brower system engineer Signalogic > > Hi everybody, > > I've got a problem with the DSP board we just designed, I hope you can help me on > this one: > > The design is mainly based on the 6711DSK, same DSP (6711 150MHz), same SDRAM > family (MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK) clock at 100MHz > through the EMIF, CE0 is used. > > My board works well, except for the SDRAMs. I am able to fill entirely my SDRAM > with data using Edit->Memory->Fill in CCS. Then i am able to read it by using > File->Data->Save in CCS still. So far it's fine. > > Problem starts to occur when i want to load my program into SDRAM (my DSP internal > mem is a 4-way cache), this error occur : "Data Verification Fail at address > 0x80000150. Please verify target memory and memory map" > > I've been trying to debug this problem by optimizing the EMIF settings for SDRAM > (SDCTL, SDTIM, SDEXT) but i have been unsuccessfull so far. > > I begin to question the hardware design. But it's should be OK as the SDRAMs are > directly connected to my DSP, it's quite a straightforward design, and as i said > based on the 6711DSK. > > Any suggestions to help me pointing the problem would be welcome, > > Thanks, > Ludo > > ------------------------- > Ludovic Tramart, DSP System Engineer > www.fulcrumvoicetech.com > FULCRUM, Hillbottom Road > High Wycombe, HP12 4HJ > Tel : +44 (0)1494 437575 > Fax: +44 (0)1494 473324 > _____________________________________ > Note: If you do a simple "reply" with your email client, only the author of this > message will receive your answer. You need to do a "reply all" if you want your > answer to be distributed to the entire group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.yahoogroups.com/group/c6x > > Other Groups: http://www.dsprelated.com |
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Reply by ●June 23, 20032003-06-23
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Ludovic- > Thanks for your reply. I did try to reduce down my ECLKIN signal to 50MHz to see the effect. But unfortunately > i still couln't load any code into my SDRAM, while my PowerOnSelfTest code (runnning from IRAM) was successfully > able to read/write on the entire memory of the SDRAMs...?! > > It's quite hard for me to separate whether it's a hardware or software problem as : > - the hardware is based on a TI design, and only minor changes have been made > - my POST code works well, and I seem to have a functionally correct board in my hands > > Any others suggestions, > Many thanks, Ludo. Well, another usual suspect is the GEL file. When you download code, CCS uses a GEL file to determine processor settings, including EMIF. When you test memory from your code, (presumably) you are setting EMIF registers beforehand. Try making sure the GEL file settings match yours. Jeff Brower system engineer Signalogic > > Hi everybody, > > > > > > I've got a problem with the DSP board we just designed, I hope you can help me on > > > this one: > > > > > > The design is mainly based on the 6711DSK, same DSP (6711 150MHz), same SDRAM > > > family (MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK) clock at 100MHz > > > through the EMIF, CE0 is used. > > > > > > My board works well, except for the SDRAMs. I am able to fill entirely my SDRAM > > > with data using Edit->Memory->Fill in CCS. Then i am able to read it by using > > > File->Data->Save in CCS still. So far it's fine. > > > > > > Problem starts to occur when i want to load my program into SDRAM (my DSP internal > > > mem is a 4-way cache), this error occur : "Data Verification Fail at address > > > 0x80000150. Please verify target memory and memory map" > > > > > > I've been trying to debug this problem by optimizing the EMIF settings for SDRAM > > > (SDCTL, SDTIM, SDEXT) but i have been unsuccessfull so far. > > > > > > I begin to question the hardware design. But it's should be OK as the SDRAMs are > > > directly connected to my DSP, it's quite a straightforward design, and as i said > > > based on the 6711DSK. > > > > > > Any suggestions to help me pointing the problem would be welcome, > > > > > > Thanks, > > > Ludo > > > > > > ------------------------- > > > Ludovic Tramart, DSP System Engineer > > > www.fulcrumvoicetech.com > > > FULCRUM, Hillbottom Road > > > High Wycombe, HP12 4HJ > > > Tel : +44 (0)1494 437575 > > > Fax: +44 (0)1494 473324 |
Reply by ●June 23, 20032003-06-23
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hi, Ludovic Tramart-: when I met such problem, I always tried to do a research on the .gel file at first, to make sure that I am using the legal memory space. And then, modify the memory map file to change the size of system memory or stack memory. It always works. I am doing work about h.263. so I don't know if it's helpful for your work. Harold UA Jeff Brower <> wrote: Ludovic Tramart- You have to separate whether it's hardware or software to start debugging. Try with SDRAM clock of 50 MHz. Still see the same results? Jeff Brower system engineer Signalogic > > Hi everybody, > > I've got a problem with the DSP board we just designed, I hope you can help me on > this one: > > The design is mainly based on the 6711DSK, same DSP (6711 150MHz), same SDRAM > family (MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK) clock at 100MHz > through the EMIF, CE0 is used. > > My board works well, except for the SDRAMs. I am able to fill entirely my SDRAM > with data using Edit->Memory->Fill in CCS. Then i am able to read it by using > File->Data->Save in CCS still. So far it's fine. > > Problem starts to occur when i want to load my program into SDRAM (my DSP internal > mem is a 4-way cache), this error occur : "Data Verification Fail at address > 0x80000150. Please verify target memory and memory map" > > I've been trying to debug this problem by optimizing the EMIF settings for SDRAM > (SDCTL, SDTIM, SDEXT) but i have been unsuccessfull so far. > > I begin to question the hardware design. But it's should be OK as the SDRAMs are > directly connected to my DSP, it's quite a straightforward design, and as i said > based on the 6711DSK. > > Any suggestions to help me pointing the problem would be welcome, > > Thanks, > Ludo > > ------------------------- > Ludovic Tramart, DSP System Engineer > www.fulcrumvoicetech.com > FULCRUM, Hillbottom Road > High Wycombe, HP12 4HJ > Tel : +44 (0)1494 437575 > Fax: +44 (0)1494 473324 > _____________________________________ > Note: If you do a simple "reply" with your email client, only the author of this > message will receive your answer. You need to do a "reply all" if you want your > answer to be distributed to the entire group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.yahoogroups.com/group/c6x > > Other Groups: http://www.dsprelated.com > > ">http://docs.yahoo.com/info/terms/ --------------------------------- |
Reply by ●June 24, 20032003-06-24
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>Hi everybody, > >I've got a problem with the DSP board we just designed, I hope you can help me on this one: > >The design is mainly based on the 6711DSK, same DSP (6711 150MHz), same SDRAM family >(MT48LC4M16A2-7E but CAS=2 instead of 3 on latest DSK) clock at 100MHz through the EMIF, CE0 is used. > >My board works well, except for the SDRAMs. I am able to fill entirely my SDRAM with data using Edit-> >Memory->Fill in CCS. Then i am able to read it by using File->Data->Save in CCS still. So far it's fine. > >Problem starts to occur when i want to load my program into SDRAM (my DSP internal mem is a 4-way cache), >this error occur : "Data Verification Fail at address 0x80000150. Please verify target memory and memory >map" > I always do a GEL reset before loading code... Also, does it work better if you close CCS, then load the code as the first thing you do (before opening any memory windows etc.)? I notice you are using CAS latency of 2 - have you done the SDRAM init comand *after* setting up the CAS latency register in the DSP, I seem to recall some TI sample code that does it the wrong way round, but they use the default of 3 cycles, so it doesn't matter. >I've been trying to debug this problem by optimizing the EMIF settings for SDRAM (SDCTL, SDTIM, SDEXT) >but i have been unsuccessfull so far. > >I begin to question the hardware design. But it's should be OK as the SDRAMs are directly connected to my >DSP, it's quite a straightforward design, and as i said based on the 6711DSK. > How are the signals looking on the PCB? You have testpoints right :-)? Hope that helps give you something to try! Cheers, Martin -- Martin Thompson BEng(Hons) CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |
