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Hi, we're running into big troubles with this errata. I increased the EMIF clock to more than half of the core clock but this seems not to help. It only decreases the probability of the error. Is there any other workaround for this problem? Another possibility would be to have the buffers located in the L2 ram. But this would decrease the performance and .... there's also a bug :(( |
L2 Cache Writeback Blocks Other EDMA Operations to EMIF
Started by ●September 5, 2003
