|
Dear all, I have already implemented EDMA-EMIF to read Frame Buffer ALL422B using asynch 8-bit which come from CMOS Sensor. I found out that the maximum speed of EDMA transfer is 4.12 Mhz and the lowest speed is 688 kHz by change the EMIF parameter. According to this maximum speed, I found that my frame rate is about 12-13 fps. This frame rate is already enough for my application, but I still would like to know whether the maximum speed of EDMA-EMIF is 4.12 Mhz when reading async 8bit or maybe there are some other experience that using EDMA- EMIF to read async device that might more than 4.12 Mhz. If I want to change my frame rate 12 fps to 30 fps, What should I do? Is there any experience using EDMA-EMIF that read for 30 fps. Thank you |
|
|
EDMA - EMIF maximum speed.
Started by ●September 23, 2003
Reply by ●September 24, 20032003-09-24
|
> rate is already enough for my application, but I still would like to > know whether the maximum speed of EDMA-EMIF is 4.12 Mhz when reading I think you should be able to go at least twice that. Using 100 MHz EMIF, you should be able to get below 10 cycles for an asynchronos read. > If I want to change my frame rate 12 fps to 30 fps, What should I > do? Is there any experience using EDMA-EMIF that read for 30 fps. Go synchronous using sync-FIFO or FPGA. Simple image capture : use BT.656 or similar sensor, connect to FPGA, connect Fpga to EMIF. Et voil! Should work (with a little piece of work in the Fpga of course). Jean-Michel MERCIER -- dsp & imaging - www.ateme.com ATEME - 26 Burospace - 91573 BIEVRES Tel : +33 (0)1 69 35 89 73 (direct) Fax : +33 (0)1 60 19 13 95 |
Reply by ●September 25, 20032003-09-25
|
>> rate is already enough for my application, but I still would like
to >> know whether the maximum speed of EDMA-EMIF is 4.12 Mhz when reading > >I think you should be able to go at least twice that. >Using 100 MHz EMIF, you should be able to get below 10 cycles >for an asynchronos read. > We got down to a 1-3-1 EMIF cycle for async read using an Altera 10KE FPGA... I was windering about doing a SSRAM interface, but never got around to it. I'm now looking at bus mastering from the FPGA to external SDRAM. >> If I want to change my frame rate 12 fps to 30 fps, What should I >> do? Is there any experience using EDMA-EMIF that read for 30 fps. > >Go synchronous using sync-FIFO or FPGA. > Agreed - we got 30fps easily that way. HTH, Martin -- Martin Thompson CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |
Reply by ●September 25, 20032003-09-25
|
Martin- > We got down to a 1-3-1 EMIF cycle for async read using an Altera > 10KE FPGA... I was windering about doing a SSRAM interface, but > never got around to it. I'm now looking at bus mastering from > the FPGA to external SDRAM. Would you put data from the C6x through the FPGA to the SDRAM, or use the FPGA and SDRAM in parallel? I've had a customer request that SDRAM data be "passed through" an FPGA for error correction / encryption purposes and we're not sure of the best approach. -Jeff |
Reply by ●September 26, 20032003-09-26
|
Henrry Andrian wrote : > Hi.. You mean that using the asynchronous 8-bit mode, EMIF could > read data for at least 8-9 MHz? Currently my EDMA setting is 3-1-2 > (for Reading). Could I know the setting for the EDMA Transfer. > > Currenlty my EDMA setting can be seen as below: > 1. FS = 0 (element synch) > 2. ESIZE = 8 Bit > 3. Data Source = Not Increament and 1D > 4. Data Destination = Increament and 1D > 5. Transfer count > Frame Count: 0x1fd > Element Count = 0x280 Obviously a 3-1-2 setting on a 100 MHz bus requires 60 ns. In some design, we are using asynchronous access between 60-100ns for example to access registers in FPGA or EPLD. So yes, you could expect a full bandwidth of 10-16 MHz. But some other points have to be taken into account. 1/ You have to write the data somewhere 2/ You have to read the data for processing The EDMA reads data at that speed, but also need to write the data somewhere => if you are writting to external SDRAM you will take time too. Counting on EDMA internal fifo + SDRAM acces, I imagine that you should add around 2 T per access. On a old 6201 system we have interfaced an asynchronous fifo at 16 MHz on 32 bits allowing 64 MB/s data rate. But as we needed to store data in SDRAM and to read it back for processing, the total bandwidth that our system could acquire and process was around 45-50 MB/s. I was wondering how your sensor is connected to EMIF because it seems that you are trying to read the video using a single EDMA run. Do you have a frame memory or are you sure that your EDMA doesn't read too fast or too slow ? May be you are using ARDY ? The most used capture system is : sensor => fifo (sync preferable) => EMIF \--- HSYNC -------------------> EXTINTn then configure EDMA as 2D, use Frame Synchronisation and use something like HSYNC to trigger line per line EDMA frame transfer. This is what we are using or our C64x based boards and similar to what is implemented in DM642 video port. Jean-Michel MERCIER -- dsp & imaging - www.ateme.com ATEME - 26 Burospace - 91573 BIEVRES Tel : +33 (0)1 69 35 89 73 (direct) Fax : +33 (0)1 60 19 13 95 > > Thx. > > --- In , "Jean-Michel MERCIER" <jm.mercier@a...> > wrote: > > > rate is already enough for my application, but I still would > like to > > > know whether the maximum speed of EDMA-EMIF is 4.12 Mhz when > reading > > > > I think you should be able to go at least twice that. > > Using 100 MHz EMIF, you should be able to get below 10 cycles > > for an asynchronos read. > > > > > If I want to change my frame rate 12 fps to 30 fps, What should > I > > > do? Is there any experience using EDMA-EMIF that read for 30 fps. > > > > Go synchronous using sync-FIFO or FPGA. > > > > Simple image capture : use BT.656 or similar sensor, connect to > FPGA, > > connect Fpga to EMIF. > > Et voil?! > > Should work (with a little piece of work in the Fpga of course). > > > > Jean-Michel MERCIER > > > > -- > > dsp & imaging - www.ateme.com > > ATEME - 26 Burospace - 91573 BIEVRES > > Tel : +33 (0)1 69 35 89 73 (direct) > > Fax : +33 (0)1 60 19 13 95 > |
|
|
Reply by ●September 26, 20032003-09-26
|
Hi.. I understand about your explanation. I will shortly explain my system. I have a planed to created imaging board using CMOS Sensor + Frame Buffer (async 8bit)+DSK6711. Because of noise problem, the async 8 bit control signal were controlled by FPGA. So the FPGA will provied two interrupt for detect one frame (Int6) and one byte(Int7) that coming from Frame buffer to DSK6711. So the DSK6711 need to detect the interrupt6 first, than will enabled the EDMA channel. After Int7 will trigger EDMA to act as event trigger. Shorty speaking, Int6 will enabled the EDMA channel and Int7 will trigger EDMA to capture one element (8bit) until 640x480 (1 frame). The Int7 frame rate is 4 Mhz, which means that every element will come out from Frame Buffer is 4 Mhz. And I am using EDMA to capture the element by using EMIF configuration 3-1-2 and will store in SDRAM. So the frame rate of the data come from Frame Buffer could be change depend on the FPGA program. Because my frame rate data come out from Frame Buffer only 4 Mhz, my frame rate only 8 fps. the EDMA parameter that I was using are 1D to 1D with Element Sync with Elemen Size is 8 byte. The completed configuration about my EDMA is: 1. FS = 0 2. Data Source, Not Increament 3. Data Destination, Increament 4. Transfer Count, Frame Count=0x1DF Element Count = 0x280 5. Link, Link to its Table 6. TCC Enabled This EDMA parameter was working. But in my opition, this configuration is not well optimized. Cause the EDMA transfer will have to wait the Int7 for every element event, So I have plan by using single interrupt as event trigger to capture a whole frame for 640x480. I have plan to optimized this EDMA configuration that using one interrupt (Int6). But I failed to the trigger to EDMA to capture the whole data. Here are the EDMA parameter settings: 1. FS=1 2. Data Source, No increament 3. Data Destination, increament 4. Transfer Count, Frame Count=0x1DF Element Count = 0x280 5. Link, Link to its Table 6. TCC Enabled This is not working. The EDMA just read for a little bit data. I dont know what wrong with this configuration. Do you think that If I am using FS=1 will change the speed of the EDMA read ? I still other thing that I am not well understand about the EDMA when using 1D or 2D. When I was using 1D-1D (FS=0), the signal of /ARE will only have one clock cycle (LOW). But when I was using 1D-2D(FS=1) the /ARE signal will have two clock cycle in LOW (LOW- HIGH-LOW). Do you know what is the two clock cycle of LOW means ? Thats all my equation and my shortly bried about my system. Best regards, Henrry > Obviously a 3-1-2 setting on a 100 MHz bus > requires 60 ns. > In some design, we are using asynchronous > access between 60-100ns for example to > access registers in FPGA or EPLD. > > So yes, you could expect a full bandwidth of 10-16 MHz. > > But some other points have to be taken into account. > 1/ You have to write the data somewhere > 2/ You have to read the data for processing > > The EDMA reads data at that speed, but also need to > write the data somewhere => if you are writting to > external SDRAM you will take time too. > Counting on EDMA internal fifo + SDRAM acces, I imagine that > you should add around 2 T per access. > > On a old 6201 system we have interfaced an asynchronous fifo > at 16 MHz on 32 bits allowing 64 MB/s data rate. But as we needed > to store data in SDRAM and to read it back for processing, > the total bandwidth that our system could acquire and process > was around 45-50 MB/s. > > I was wondering how your sensor is connected to EMIF > because it seems that you are trying to read the video > using a single EDMA run. Do you have a frame memory > or are you sure that your EDMA doesn't read too fast > or too slow ? > May be you are using ARDY ? > > The most used capture system is : > sensor => fifo (sync preferable) => EMIF > \--- HSYNC -------------------> EXTINTn > > then configure EDMA as 2D, use Frame Synchronisation > and use something like HSYNC to trigger line per line > EDMA frame transfer. > > This is what we are using or our C64x based boards > and similar to what is implemented in DM642 video port. > Jean-Michel MERCIER > > -- > dsp & imaging - www.ateme.com > ATEME - 26 Burospace - 91573 BIEVRES > Tel : +33 (0)1 69 35 89 73 (direct) > Fax : +33 (0)1 60 19 13 95 > > > > > > Thx. > > > > --- In , "Jean-Michel MERCIER" <jm.mercier@a...> > > wrote: > > > > rate is already enough for my application, but I still would > > like to > > > > know whether the maximum speed of EDMA-EMIF is 4.12 Mhz when > > reading > > > > > > I think you should be able to go at least twice that. > > > Using 100 MHz EMIF, you should be able to get below 10 cycles > > > for an asynchronos read. > > > > > > > If I want to change my frame rate 12 fps to 30 fps, What should > > I > > > > do? Is there any experience using EDMA-EMIF that read for 30 fps. > > > > > > Go synchronous using sync-FIFO or FPGA. > > > > > > Simple image capture : use BT.656 or similar sensor, connect to > > FPGA, > > > connect Fpga to EMIF. > > > Et voil?! > > > Should work (with a little piece of work in the Fpga of course). > > > > > > Jean-Michel MERCIER > > > > > > -- > > > dsp & imaging - www.ateme.com > > > ATEME - 26 Burospace - 91573 BIEVRES > > > Tel : +33 (0)1 69 35 89 73 (direct) > > > Fax : +33 (0)1 60 19 13 95 > > |
|
|
Reply by ●September 29, 20032003-09-29
|
Hi Jeff, >> We got down to a 1-3-1 EMIF cycle for async read using an Altera >> 10KE FPGA... I was windering about doing a SSRAM interface, but >> never got around to it. I'm now looking at bus mastering from >> the FPGA to external SDRAM. > >Would you put data from the C6x through the FPGA to the SDRAM, or use the FPGA and >SDRAM in parallel? I've had a customer request that SDRAM data be "passed through" >an FPGA for error correction / encryption purposes and we're not sure of the best >approach. > I'd use the SDRAM and FPGA in parallel, as I don;t want to do anything more to the data once it's in SDRAM - passing the data through the FPGA will put even more latency on the access :-( If you need to do error correction or encryption, then I think you probably have to pass it through unforunately... Cheers, Martin -- Martin Thompson CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |
Reply by ●September 29, 20032003-09-29
|
HI Henrry, > This EDMA parameter was working. But in my opition, this > configuration is not well optimized. Cause the EDMA transfer will Yes. On C64x (but probably valid also for C6711), the EDMA controller need around 30 CPU cycles to schedule its 1st read transfer from the time it receive the triggering event. And you may still have to add a few delay to gain the bus if the burst of another transfer is already performing on the bus (EDMA/CPU priority scheduling is done on burst frontiers). So clearly, triggering the EDMA at byte level is not a good idea. As you have a frame buffer, I believe that you can start reading the frame when the frame data is all in the frame buffer so you won't have any synchronization problems with the capture process : you can read as fast as you can as all the datas already in frame buffer. But the problem is that EDMA always require a synchronization : either Frame or Element in 1D mode. In 2D, it is Array or Block. So if you want to use a N x M transfer in a single EDMA request, without using partial sync event, you must use a 2D transfer, Block Synchronized. I must admit that for me too it is always tricky to choose between 1D/2D, block/array, etc.. so I have a little test program (see it included). For me the configuration that match your need is : EDMA_configArgs( hEdma, // hEdma, EDMA_OPT_RMK( // opt, EDMA_OPT_PRI_HIGH, //pri, EDMA_OPT_ESIZE_8BIT, //esize, // Source is an single address( hardware port, fifo) EDMA_OPT_2DS_NO, //ds2, EDMA_OPT_SUM_NONE, //sum, EDMA_OPT_2DD_YES, //dd2, EDMA_OPT_DUM_INC, //dum, EDMA_OPT_TCINT_YES, //tcint, EDMA_OPT_TCC_OF(tcc), //tcc, EDMA_OPT_LINK_NO, //link, EDMA_OPT_FS_YES //fs ), EDMA_SRC_RMK( Source ), //src, EDMA_CNT_RMK( // cnt, DEST_HEIGHT-1, // frmcnt, DEST_WIDTH // elecnt ), EDMA_DST_RMK( Dest ), //dst, EDMA_IDX_RMK( //idx, 0, //frmidx, 0 //eleidx ), EDMA_RLD_RMK( // rld 0, //elerld, 0 //link ) ); > I still other thing that I am not well understand about the EDMA > when using 1D or 2D. When I was using 1D-1D (FS=0), the signal > of /ARE will only have one clock cycle (LOW). But when I was using > 1D-2D(FS=1) the /ARE signal will have two clock cycle in LOW (LOW- > HIGH-LOW). Do you know what is the two clock cycle of LOW means ? No idea yet. I will ask to a hardware guru. Jean-Michel MERCIER -- dsp & imaging - www.ateme.com ATEME - 26 Burospace - 91573 BIEVRES Tel : +33 (0)1 69 35 89 73 (direct) Fax : +33 (0)1 60 19 13 95 | |||
| |||
|
|
Reply by ●September 29, 20032003-09-29
|
Henry wrote : > I still other thing that I am not well understand about the EDMA > when using 1D or 2D. When I was using 1D-1D (FS=0), the signal > of /ARE will only have one clock cycle (LOW). But when I was using > 1D-2D(FS=1) the /ARE signal will have two clock cycle in LOW (LOW- > HIGH-LOW). Do you know what is the two clock cycle of LOW means ? This seems weird to our hardware guys. Could you check the errata of the DSP. They remember that there was a issue with setting 2 as hold value on asynchronous access on some 64x DSPs so they wnder if this true also on 6711. Jean-Michel MERCIER -- dsp & imaging - www.ateme.com ATEME - 26 Burospace - 91573 BIEVRES Tel : +33 (0)1 69 35 89 73 (direct) Fax : +33 (0)1 60 19 13 95 |
