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I think I have the answer now, courtesy of TI Technical support and a little research of my own. The problem seems to be that the CPU, which controls the operation of the cache, does not know that the EDMA has altered the destination buffer and does not update its cache to reflect it. Examining the contents of the buffer using CCS then just reads the cache (which contains my original default values). Doing an L2 cache flush (manually using CCS) before examining the buffer in CCS should then mean that the correct data can be seen (I haven't tried this yet). Disabling the L2 cache (and even modifying its size) also resulted in correct operation. My solution is to move my destination buffer into internal memory (there are other reasons for me to do this as well). Good luck ! Gary --- In c6x@y..., Andrew Elder <andrew_elder@b...> wrote: > > Gabor, > > I assume you are taking care to do an L2 cache flush before > running the Tx side ? I got caught out with that one ! > > Andrew |
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EDMA under DSP/BIOS II
Started by ●January 23, 2001
Reply by ●January 29, 20012001-01-29
Reply by ●January 30, 20012001-01-30
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--- In c6x@y..., gary.halfyard@b... wrote: > Doing an L2 cache flush (manually using CCS) before examining the > buffer in CCS should then mean that the correct data can be seen (I > haven't tried this yet). I have found my bugs: - instead of CACHE_Flush(CACHE_L2) I should invoke CACHE_Clean(CACHE_L2) CSL function. CACHE_Flush() does not invalidate data in cache, therefore cache hit can occur at later accesses. This was my case: altough the buffer was flushed but I have accessed its data directly in cache. - CACHE_Flush() was invoked not only after buffer initialization but e.g. in Transmit Complete ISR. This is wrong: CACHE_Flush() can overwite the buffer by its previous cached content. Thanks & take care Gabor |
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Reply by ●February 1, 20012001-02-01
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Last, but not least: I have found, that TI has a new version of its Application Report "TMS320C6000 McBSP as a TDM Highway" (SPRA491A - Updated: 09/11/2000) (http://www.ti.com/sc/docs/psheets/abstract/apps/spra491a.htm) The update enhances the original example code with - DSP/BIOS - using McBSP with EDMA - CSL - where to use CASH_flush(), CASH_clean() Gabor |
