FollowUp -> Fw: DM642 VideoPort: VP_open doesnt return

Started by April 14, 2005

finally one step forward...:

The problem is caused by the FPGA that is on the EVM642 board. This is
between the VideoPort and the SAA7105 video encoder. If this FPGA is not
initialized correctly, some clocks are missing and VP dosent finish its
reset... (see spru295.pdf)

best regards,


--- Weitergeleitete Nachricht / Forwarded Message ---
Subject: [c6x] Fw: DM642 VideoPort: VP_open doesnt return Another thing I found out:

I extracted the source of VP_open from the csl6000.src with ar6x and
compiled it locally with my small application. When VP_open is called with
VP_OPEN_RESET, the following code is executed:

/* Enable video port in PCR register if it is not */


/* Wait for reset to complete */

well - and the last while is an infinite loop when the VPCTL bit is not
reset to 0 again. I wonder why TI hasnt implemented a timeout or something
to make the function exit when an error happens...

In my case, the VPRST bit in VPCTL is set to 1 and remains 1 forever, the
reset is never finished, thats why VP_open call hangs.

Whats required to make the VP-Reset finish?



> ===============================================================
> Hi,
> In another posting some hours back, I have described a problem
> the DM642s VideoPort. I have seen another quite strange behaviour, maybe
> someone had this before...:
> 1.) powerOn
> 2.) download small application that enables videoPort in the PERCFG
> (CHIP_config) and
> 3.) call VP_open(anyPortNr, VP_OPEN_RESET). This call doesnt return.
> Again - like described yesterday - when I download the VGA_DISPLAY sample,
> reset the CPU from CCS and reload my application, the VP_open returns.
> Anyone has observed a similar hanging of the VP_open? What was the
> There is something required apart from enabling the videoPort in the
> register to make the VideoPort active, some setting that survives a 'Reset
> CPU' from CCS - what could this be?
> best regards,
> thomas

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