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Hi, I'm having problems accessing SDRAM in a reasonable time. I read on the periperal guide that consequent access to SDRAM should happen in bursts of 4 words. I understood they are talking about 32-bit words. Is this correct? Because I tried to look at the signals (Chip enable, write enable, read enable) with the oscilloscope, but I cannot see any burst! I wrote simple assembler code to write 16 words to SDRAM, and I observe 16 memory accesses (expected 16/4=4). Each memory access takes 1 EMIF clock cycle. The time between each access is about 10 EMIF clock cycles. I don't understand what the dsp is doing during tha time. Has anybody else experienced problems like this with memory access? Am I doing anything wrong? TIA Federica Legger |
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SDRAM memory access with 6711 DSK
Started by ●February 7, 2002
Reply by ●February 11, 20022002-02-11
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Federica,
The CPU does not know that there will be 15 more
write accesses to
If you can instead write the data to SRAM address
space and then program
I guess in your example, SDRAM space is non-cacheable
or else the CPU
Subrangshu
fedelegger wrote: Hi,
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