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Hi, I'm wondering, has anyone experience using the McBSP on speeds as high as 75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the maximum speed is on the McBSP if it uses the internal clock source. In the TI peripheral guide, it is stated that "The maximum bit rate for the C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " But I'm not sure I can use more than 75MHz... Any ideas? Jan |
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McBSPs on 100MHz
Started by ●February 26, 2002
Reply by ●February 27, 20022002-02-27
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Jan- >I'm wondering, has anyone experience using the McBSP on speeds as high as >75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >maximum speed is on the McBSP if it uses the internal clock source. > >In the TI peripheral guide, it is stated that "The maximum bit rate for the >C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " > >But I'm not sure I can use more than 75MHz... We are working with multiple C6203 device boards, running at 300 MHz, but we have not tried the McBSPs at rates higher than around 24 Mbps. What about X-Bus? Do you have Rev. 3.0 silicon yet? Have you tried at the rated 75 MHz? Jeff Brower DSP sw/hw engineer Signalogic |
Reply by ●February 27, 20022002-02-27
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Jan, The maximum bit rate for the C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz (P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. So @300MHz use otherwise the CLK divider or a external clock source for having it at 100MHz. Also take care that the McBSP can only be in master mode with 100MHz. Best regards, Ferry Clasquin European - PIC -----Original Message----- From: Asselman Jan [mailto:] Sent: Tuesday, February 26, 2002 5:50 PM To: C6x yahoo newsgroup (E-mail) Subject: [c6x] McBSPs on 100MHz Hi, I'm wondering, has anyone experience using the McBSP on speeds as high as 75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the maximum speed is on the McBSP if it uses the internal clock source. In the TI peripheral guide, it is stated that "The maximum bit rate for the C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " But I'm not sure I can use more than 75MHz... Any ideas? Jan _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://www.dsprelated.com ">http://docs.yahoo.com/info/terms/ |
Reply by ●February 27, 20022002-02-27
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I've done 75Mhz on a C6711 @150MHz core clock. Cheers, Martin -- Martin Thompson BEng(Hons) CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4GW. UK Tel: +44 (0)121-627-3569 - >>> Asselman Jan <> 26 February 2002 16:50:01 >>> Hi, I'm wondering, has anyone experience using the McBSP on speeds as high as 75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the maximum speed is on the McBSP if it uses the internal clock source. In the TI peripheral guide, it is stated that "The maximum bit rate for the C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " But I'm not sure I can use more than 75MHz... Any ideas? Jan _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://www.dsprelated.com ">http://docs.yahoo.com/info/terms/ |
Reply by ●February 27, 20022002-02-27
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Hi Jeff, We use 2 McBSPs to connect to a FPGA. The FPGA-people don't like a lot of wires coming in, you know... ;-) Also, the HPI (part of the X bus) is reserved for interfacing to a PowerPC... Are the McBSPs taking lots of DMA&CPU time? Cheers, Jan -----Original Message----- From: Jeff Brower [mailto:] Sent: woensdag 27 februari 2002 0:47 To: Asselman Jan Cc: Subject: Re: [c6x] McBSPs on 100MHz Jan- >I'm wondering, has anyone experience using the McBSP on speeds as high as >75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >maximum speed is on the McBSP if it uses the internal clock source. > >In the TI peripheral guide, it is stated that "The maximum bit rate for the >C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " > >But I'm not sure I can use more than 75MHz... We are working with multiple C6203 device boards, running at 300 MHz, but we have not tried the McBSPs at rates higher than around 24 Mbps. What about X-Bus? Do you have Rev. 3.0 silicon yet? Have you tried at the rated 75 MHz? Jeff Brower DSP sw/hw engineer Signalogic |
Reply by ●February 27, 20022002-02-27
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>Martin, > >Did you encountered problems on that? > Not so far. >On the C6711 you can use the EDMA, isn't it? On the C6203 it is still the >DMA... > >Do you have any idea about the CPU-load you had? > Not too heavily loaded, probably around 50%. >I'm asking this 'cause I'm not sure if the C6203 can handle 2 full-speed >McBSP@100MHz connected to DMA... > That would depend on things like frame-size, whether it's going to external memory and so forth I imagine. Cheers, Martin > >-----Original Message----- >From: Martin.J Thompson [mailto:] >Sent: woensdag 27 februari 2002 9:29 >To: ; >Subject: Re: [c6x] McBSPs on 100MHz >I've done 75Mhz on a C6711 @150MHz core clock. > >Cheers, >Martin > >-- >Martin Thompson BEng(Hons) CEng MIEE >TRW Conekt >Stratford Road, Solihull, B90 4GW. UK >Tel: +44 (0)121-627-3569 - >>>> Asselman Jan <> 26 February 2002 16:50:01 >>>> >Hi, > >I'm wondering, has anyone experience using the McBSP on speeds as high as >75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >maximum speed is on the McBSP if it uses the internal clock source. > >In the TI peripheral guide, it is stated that "The maximum bit rate for the >C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " > >But I'm not sure I can use more than 75MHz... > >Any ideas? > >Jan >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of >this message will receive your answer. You need to do a "reply all" if you >want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.yahoogroups.com/group/c6x > >Other Groups: http://www.dsprelated.com >">http://docs.yahoo.com/info/terms/ > > >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of >this message will receive your answer. You need to do a "reply all" if you >want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.yahoogroups.com/group/c6x > >Other Groups: http://www.dsprelated.com >">http://docs.yahoo.com/info/terms/ > |
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Reply by ●February 27, 20022002-02-27
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All, The C6711 has a silicon design bug that can cause EDMA transfers to be missed. The problem occurs when the cache controller takes over the EDMA controller (it always has priority) thereby preventing EDMA <-> McBSP transfers. If code generates an L1P miss followed by several L2 cache misses the cache controller can take over the EDMA subsystem. An example of the sort of operation that can cause this is memcpy(). Our company spent about 6 months tracking this one down. I'd hate someone else to have to repeat the experience. Andrew E. At 01:29 PM 2/27/02 +0000, Martin.J Thompson wrote: >>Martin, >> >>Did you encountered problems on that? >> > >Not so far. > >>On the C6711 you can use the EDMA, isn't it? On the C6203 it is still the >>DMA... >> >>Do you have any idea about the CPU-load you had? >> > >Not too heavily loaded, probably around 50%. > >>I'm asking this 'cause I'm not sure if the C6203 can handle 2 full-speed >>McBSP@100MHz connected to DMA... >> > >That would depend on things like frame-size, whether it's going to external >memory and so forth I imagine. > >Cheers, >Martin > >> >>-----Original Message----- >>From: Martin.J Thompson [mailto:] >>Sent: woensdag 27 februari 2002 9:29 >>To: ; >>Subject: Re: [c6x] McBSPs on 100MHz >> >> >>I've done 75Mhz on a C6711 @150MHz core clock. >> >>Cheers, >>Martin >> >>-- >>Martin Thompson BEng(Hons) CEng MIEE >>TRW Conekt >>Stratford Road, Solihull, B90 4GW. UK >>Tel: +44 (0)121-627-3569 - >> >> >>>>> Asselman Jan <> 26 February 2002 16:50:01 >>>>> >>Hi, >> >>I'm wondering, has anyone experience using the McBSP on speeds as high as >>75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >>maximum speed is on the McBSP if it uses the internal clock source. >> >>In the TI peripheral guide, it is stated that "The maximum bit rate for the >>C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " >> >>But I'm not sure I can use more than 75MHz... >> >>Any ideas? >> >>Jan >> >> |
Reply by ●February 27, 20022002-02-27
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Does TI have any technical documentation on this silicon bug? I'm working on a project that could be adversely affected by this. Steve -----Original Message----- From: Andrew Elder [mailto:] Sent: Wednesday, February 27, 2002 10:06 AM To: Subject: RE: [c6x] McBSPs on 100MHz All, The C6711 has a silicon design bug that can cause EDMA transfers to be missed. The problem occurs when the cache controller takes over the EDMA controller (it always has priority) thereby preventing EDMA <-> McBSP transfers. If code generates an L1P miss followed by several L2 cache misses the cache controller can take over the EDMA subsystem. An example of the sort of operation that can cause this is memcpy(). Our company spent about 6 months tracking this one down. I'd hate someone else to have to repeat the experience. Andrew E. At 01:29 PM 2/27/02 +0000, Martin.J Thompson wrote: >>Martin, >> >>Did you encountered problems on that? >> > >Not so far. > >>On the C6711 you can use the EDMA, isn't it? On the C6203 it is still the >>DMA... >> >>Do you have any idea about the CPU-load you had? >> > >Not too heavily loaded, probably around 50%. > >>I'm asking this 'cause I'm not sure if the C6203 can handle 2 full-speed >>McBSP@100MHz connected to DMA... >> > >That would depend on things like frame-size, whether it's going to external >memory and so forth I imagine. > >Cheers, >Martin > >> >>-----Original Message----- >>From: Martin.J Thompson [mailto:] >>Sent: woensdag 27 februari 2002 9:29 >>To: ; >>Subject: Re: [c6x] McBSPs on 100MHz >> >> >>I've done 75Mhz on a C6711 @150MHz core clock. >> >>Cheers, >>Martin >> >>-- >>Martin Thompson BEng(Hons) CEng MIEE >>TRW Conekt >>Stratford Road, Solihull, B90 4GW. UK >>Tel: +44 (0)121-627-3569 - >> >> >>>>> Asselman Jan <> 26 February 2002 16:50:01 >>>>> >>Hi, >> >>I'm wondering, has anyone experience using the McBSP on speeds as high as >>75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >>maximum speed is on the McBSP if it uses the internal clock source. >> >>In the TI peripheral guide, it is stated that "The maximum bit rate for the >>C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " >> >>But I'm not sure I can use more than 75MHz... >> >>Any ideas? >> >>Jan >> >> _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://www.dsprelated.com ">http://docs.yahoo.com/info/terms/ |
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Reply by ●February 28, 20022002-02-28
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Andrew, is this silicon bug documented in any 6711 Silicon Errata? Thanks, Gabor > The C6711 has a silicon design bug that can cause EDMA > transfers to be missed. > The problem occurs when the cache controller takes over the > EDMA controller (it > always has priority) thereby preventing EDMA <-> McBSP > transfers. If code > generates an L1P miss followed by several L2 cache misses the > cache controller > can take over the EDMA subsystem. An example of the sort of > operation that can > cause this is memcpy(). > > Our company spent about 6 months tracking this one down. I'd > hate someone else > to have to repeat the experience. > > Andrew E. |
Reply by ●February 28, 20022002-02-28
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I haven't yet seen any public documentation on the issue. I've just sent TI an email to try to get a reference number (or something) for the issue. Andrew At 05:23 PM 2/27/02 -0500, Steve Thornhill wrote: >Does TI have any technical documentation on this silicon bug? >I'm working on a project that could be adversely affected by this. > >Steve > >-----Original Message----- >From: Andrew Elder [mailto:] >Sent: Wednesday, February 27, 2002 10:06 AM >To: >Subject: RE: [c6x] McBSPs on 100MHz > >All, > >The C6711 has a silicon design bug that can cause EDMA transfers to be missed. >The problem occurs when the cache controller takes over the EDMA controller (it >always has priority) thereby preventing EDMA <-> McBSP transfers. If code >generates an L1P miss followed by several L2 cache misses the cache controller >can take over the EDMA subsystem. An example of the sort of operation that can >cause this is memcpy(). > >Our company spent about 6 months tracking this one down. I'd hate someone else >to have to repeat the experience. > >Andrew E. > >At 01:29 PM 2/27/02 +0000, Martin.J Thompson wrote: >>>Martin, >>> >>>Did you encountered problems on that? >>> >> >>Not so far. >> >>>On the C6711 you can use the EDMA, isn't it? On the C6203 it is still the >>>DMA... >>> >>>Do you have any idea about the CPU-load you had? >>> >> >>Not too heavily loaded, probably around 50%. >> >>>I'm asking this 'cause I'm not sure if the C6203 can handle 2 full-speed >>>McBSP@100MHz connected to DMA... >>> >> >>That would depend on things like frame-size, whether it's going to external >>memory and so forth I imagine. >> >>Cheers, >>Martin >> >>> >>>-----Original Message----- >>>From: Martin.J Thompson [mailto:] >>>Sent: woensdag 27 februari 2002 9:29 >>>To: ; >>>Subject: Re: [c6x] McBSPs on 100MHz >>> >>> >>>I've done 75Mhz on a C6711 @150MHz core clock. >>> >>>Cheers, >>>Martin >>> >>>-- >>>Martin Thompson BEng(Hons) CEng MIEE >>>TRW Conekt >>>Stratford Road, Solihull, B90 4GW. UK >>>Tel: +44 (0)121-627-3569 - >>> >>> >>>>>> Asselman Jan <> 26 February 2002 16:50:01 >>>>>> >>>Hi, >>> >>>I'm wondering, has anyone experience using the McBSP on speeds as high as >>>75,100 or 150MHz. I'm using the C6203@300MHz. I try to figure out what the >>>maximum speed is on the McBSP if it uses the internal clock source. >>> >>>In the TI peripheral guide, it is stated that "The maximum bit rate for the >>>C6203B/03C device is 100 Mbps or CPU/2 (the slower of the two). " >>> >>>But I'm not sure I can use more than 75MHz... >>> >>>Any ideas? >>> >>>Jan >>> >> >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of >this message will receive your answer. You need to do a "reply all" if you >want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.yahoogroups.com/group/c6x > >Other Groups: http://www.dsprelated.com >">http://docs.yahoo.com/info/terms/ > > >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of >this message will receive your answer. You need to do a "reply all" if you >want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.yahoogroups.com/group/c6x > >Other Groups: http://www.dsprelated.com >">http://docs.yahoo.com/info/terms/ |
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