understand .T address Path in Feedback

Started by wass...@gmail.com April 7, 2006
Hi DSPies,

I have some C codes that I rewrite in linear assembly to get the best performance in terms of cyles count. I'm working with C64.
I end up with a .sa having this software pipeline information on its generated .asm


Loop source line : 32
Loop closing brace source line : 55
Known Minimum Trip Count : 4
Known Maximum Trip Count : 8
Known Max Trip Count Factor : 4
Loop Carried Dependency Bound(^) : 3
Unpartitioned Resource Bound : 2
Partitioned Resource Bound(*) : 4
Resource Partition:
A-side B-side
.L units 1 1
.S units 1 0
.D units 2 2
.M units 2 2
.X cross paths 1 3
.T address paths 4* 2
Long read paths 0 0
Long write paths 0 0
Logical ops (.LS) 1 0 (.L or .S unit)
Addition ops (.LSD) 1 3 (.L or .S or .D unit)
Bound(.L .S .LS) 2 1
Bound(.L .S .D .LS .LSD) 2 2

Searching for software pipeline schedule at ...
ii = 4 Schedule found with 4 iterations in parallel

Epilog not removed
Collapsed epilog stages : 0

Prolog not entirely removed
Collapsed prolog stages : 2

Minimum required memory pad : 0 bytes

Minimum safe trip count : 3

As you can see the limiting factor is .T on the A side:4.
the problem is when I try to interpret that value I find that it is greater than .D memory access values wich is exactly 2 on the A side(ldw and ldnw)
The TI docs say that it is due to bad ressource partionning between the two sides but you can also see that the partioning is even between them.

Can Somebody help me. I'm getting tired from this lack of explanation in TI's docs.

Thanks in Advance