EMIFA conflict on DM642

Hi all,
I've a conflict problem on my board, this is the situation:
I've a DM642 DSP, SDRAM and FPGA on my board.
SDRAM is mapped on EMIFA CE0
FPGA is mapped on EMIFA CE1

I use EDMA controller to transfer my data from FPGA to SDRAM, with
this configuration:
opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
src: 0x90000000 // FPGA address
cnt: 20
dst: 0x80001000 // SDRAM address
idx: 0
rld: 0
in this configuration the data transported in SDRAM are wrong!!!

Otherwise, If I put the FPGA data in internal memory, everything is
OK!! for example:

opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
src: 0x90000000 // FPGA address
cnt: 20
dst: 0x0001A120 // Internal DSP memory
idx: 0
rld: 0

of sure, there is a conflict between EMIF signals,
have you ever seen this problem?
Pass through Internal memory is to slow for my application!
How can I solve it?

Thanks you
Gio Start a New Thread

Gio,

It is likely that your FPGA timings are wrong and
that the FPGA does not release the bus in-time.

How is your FPGA interfaced to the EMIF ? in ASYNC
or SYNC mode ?

Note that with regards to your concern of going through ISRAM
is worng because anyhow the DMA is doing exactly that :
read cycles from FPGA to internal DMA FIFO then
write cycles from internal DMA FIFO to SDRAM.
So chaining DMA would not change much performance
if you do this properly.

But anyhow, you probably have a HW design issue
(or EMIF timing settings issue).

Note that if you want to avoid this copy through internal fifo
you need to use the PDT mode of the DMA. In PDT mode,
the DMA generates a read cycle on the source devide
but does not take care of the incoming data. At the same time
it assert the PDT signal and it is up to your hardware to use
this to generate simultaneously a write cycle to the SDRAM.

We have used PDT from SDRAM to FPGA as in that case the
DSP generates the SDRAM read-cycles so generating FPGA
write-cycles from PDT signal is easy. In the other direction,
generating SDRAM write-cycles is much more tricky as the
DSP will NOT generates the addresses cycles for the SDRAM.
Regards,

jean-michel.

----- Original Message -----
From: "presciutti_dgl2k"
To:
Sent: Tuesday, September 05, 2006 1:11 PM
Subject: [c6x] EMIFA conflict on DM642
> Hi all,
> I've a conflict problem on my board, this is the situation:
> I've a DM642 DSP, SDRAM and FPGA on my board.
> SDRAM is mapped on EMIFA CE0
> FPGA is mapped on EMIFA CE1
>
> I use EDMA controller to transfer my data from FPGA to SDRAM, with
> this configuration:
> opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
> src: 0x90000000 // FPGA address
> cnt: 20
> dst: 0x80001000 // SDRAM address
> idx: 0
> rld: 0
> in this configuration the data transported in SDRAM are wrong!!!
>
> Otherwise, If I put the FPGA data in internal memory, everything is
> OK!! for example:
>
> opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
> src: 0x90000000 // FPGA address
> cnt: 20
> dst: 0x0001A120 // Internal DSP memory
> idx: 0
> rld: 0
>
> of sure, there is a conflict between EMIF signals,
> have you ever seen this problem?
> Pass through Internal memory is to slow for my application!
> How can I solve it?
>
> Thanks you
> Gio
> Start a New Thread

Thanks you Jean-Michel,
thanks to your observation I solved my problem. FPGA does not release
the bus, I correct the FPGA code and everything is right.
Due to our HW design, we can't use PDT mode, we must use internal DMA
FIFO.
Hope this experience can help someone else too.

Thanks again
Gio
--- In c..., "Jean-Michel Mercier"
wrote:
>
> Gio,
>
> It is likely that your FPGA timings are wrong and
> that the FPGA does not release the bus in-time.
>
> How is your FPGA interfaced to the EMIF ? in ASYNC
> or SYNC mode ?
>
> Note that with regards to your concern of going through ISRAM
> is worng because anyhow the DMA is doing exactly that :
> read cycles from FPGA to internal DMA FIFO then
> write cycles from internal DMA FIFO to SDRAM.
> So chaining DMA would not change much performance
> if you do this properly.
>
> But anyhow, you probably have a HW design issue
> (or EMIF timing settings issue).
>
> Note that if you want to avoid this copy through internal fifo
> you need to use the PDT mode of the DMA. In PDT mode,
> the DMA generates a read cycle on the source devide
> but does not take care of the incoming data. At the same time
> it assert the PDT signal and it is up to your hardware to use
> this to generate simultaneously a write cycle to the SDRAM.
>
> We have used PDT from SDRAM to FPGA as in that case the
> DSP generates the SDRAM read-cycles so generating FPGA
> write-cycles from PDT signal is easy. In the other direction,
> generating SDRAM write-cycles is much more tricky as the
> DSP will NOT generates the addresses cycles for the SDRAM.
> Regards,
>
> jean-michel.
> ----- Original Message -----
> From: "presciutti_dgl2k"
> To:
> Sent: Tuesday, September 05, 2006 1:11 PM
> Subject: [c6x] EMIFA conflict on DM642
> > Hi all,
> > I've a conflict problem on my board, this is the situation:
> > I've a DM642 DSP, SDRAM and FPGA on my board.
> > SDRAM is mapped on EMIFA CE0
> > FPGA is mapped on EMIFA CE1
> >
> > I use EDMA controller to transfer my data from FPGA to SDRAM, with
> > this configuration:
> > opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
> > src: 0x90000000 // FPGA address
> > cnt: 20
> > dst: 0x80001000 // SDRAM address
> > idx: 0
> > rld: 0
> > in this configuration the data transported in SDRAM are wrong!!!
> >
> > Otherwise, If I put the FPGA data in internal memory, everything
is
> > OK!! for example:
> >
> > opt: 0x44BE2001h // Block Synchronized 2D-to-2D Transfer
> > src: 0x90000000 // FPGA address
> > cnt: 20
> > dst: 0x0001A120 // Internal DSP memory
> > idx: 0
> > rld: 0
> >
> > of sure, there is a conflict between EMIF signals,
> > have you ever seen this problem?
> > Pass through Internal memory is to slow for my application!
> > How can I solve it?
> >
> > Thanks you
> > Gio
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> Start a New Thread