Cache misses

Hi All,
I am implementing h.264 on ti dm642. There is a problem for encoder design.

Actually my code is running fine. But from profile data that i got is reason to concern. From profiling i come to know that data and instruction cache misses on L1, L2 both are 100%. I am surprised how it could be 100% if simulator is simulating cache behavior in "functional" simulation configuration. It is same for "cycle accurate" simulation as well.

I have enabled L2 cache. But did not found any method to enable L1 cache.
I am doing just simulation and have no any such board to test on real time. I am now optimizing my encoder.

##Any suggations requested for enhancing cache performance.

##Also can anybody tell me areas where i can optimize my encoder cycle count performance.

Thanking You
nilesh Start a New Thread

Hi,

Optimizing cache performance:
On DM642 L1 Data/Program cache is always enabled. You
have to fine tune L2 cache size to increase
performance. To optimize program cache hits, group
program code into sections accroding to program flow.
For example, place all motion estimation modules in
one section and deblocking modules in other. On L1P
and L2 miss, the CPU fetches L2 cache line size
program code. On grouping modules into a section
increases cache hits. The same applies to data cache
too...

Optimizing H.264 encoder:
There are many ti documents talks about optimizing a
video codec on DM642 platform, you can refer these
doc's and apply the same principles for your codec.
The following steps may help,
1. compiler switches, pragma's, intrinsics.
2. critical data sections in internal memory.
3. Linear/schedule assembly.
4. IDMA/EDMA/QDMA for data transfer.

Thanks and regards,
-Lakshman

--- "H.264encoderondm642"
wrote:

> > Date: Mon, 20 Nov 2006 22:40:09 -0800 (PST)
> From: "H.264encoderondm642"
> Subject: Re: [c6x] Cache misses
> To: "H.264encoderondm642" Hi All,
> Here's code that i have added in my main encoder
> function (main function)=> CSL_init();
> CACHE_enableCaching(CACHE_EMIFA_CE00);
> CACHE_setL2Mode(CACHE_32KCACHE);
>
> I this correct to write it in that place?? or before
> main fuction getting called ? if thats case then
> where it should be (above line code)??
> and i have added this to build options=> -d"CHIP_DM642"
>
> I think this may help u to figure out my problem.
> "H.264encoderondm642" wrote:
> Hi All,
> I am implementing h.264 on ti dm642. There is a
> problem for encoder design.
>
> Actually my code is running fine. But from profile
> data that i got is reason to concern. From profiling
> i come to know that data and instruction cache
> misses on L1, L2 both are 100%. I am surprised how
> it could be 100% if simulator is simulating cache
> behavior in "functional" simulation configuration.
> It is same for "cycle accurate" simulation as well.
>
> I have enabled L2 cache. But did not found any
> method to enable L1 cache.
> I am doing just simulation and have no any such
> board to test on real time. I am now optimizing my
> encoder.
>
> ##Any suggations requested for enhancing cache
> performance.
>
> ##Also can anybody tell me areas where i can
> optimize my encoder cycle count performance.
>
> Thanking You
> nilesh
> Start a New Thread