Greetings all, I've been trying to use the PCM3003 daughtercard (a.k.a. TMDX326040A) with the 6711DSK, but have bumped into a problem here. Maybe you folks could provide me with an insight. I'm trying to receive/transmit data from/to the PCM3003 daughter card via McBSP1 with the transmission/reception triggered by an external interrupt, coming from the daughtercard. I've tried a sample "loopback" code (by Michael Morris, posted on the TI site), but I seem to have a different daughterboard than the one specified there (the jumper definitions don't match his). Is anyone in the group using such daughtercard with McBSP1/EDMA/non-polling? If so, is there a simple example program that you could send (or reply with the link) us here? Thank you in advance for your help, BrunoK |
|
Using PCM3003 daughtercard and c6711DSK
Started by ●June 28, 2002
Reply by ●July 2, 20022002-07-02
Hi, c6xers, I am newer to c6000 and I meet problem in test McBSP. I connect two c6201 on Pentek 4290 through McBSP0 as: CLKX<->CLKR, FSR<->FSR, DR<->DX. I use the example of spra455a, spra488b, spra551a and make some change: each DSP transfer and recieve 256 32bit words. I transfer 0 to 255. In the one that I start first I get 0xFFFFFFFF, 0x00000000(0) to 0x000000FE(254) and in the one I start second I get all 0x000000FF. I have test with poll and interrupt mode of McBSP as well as the DMA mode the example use. I found that: 1. XRDY seems to have no use: if I start the transmitter only it write along till end in spite whether the receiver work or not. 2. At the reciever if I enable SRGR(GRST=1) before reading McBSP I will get a 0 or 0xffffffff first,i.e., no matter the transmitter work or not the RRDY is set after out of reset. 3. If I enable frame sync generator before write McBSP I will get a zero first at the reciever. If I enable frame sync generator after a write to McBSP there is no this problem. 4. After the transmision I must disable frame sync generator to let another transmission can work. Here is the program I used(DMA mode, run on both DSPs): // main function file mcbsp_dsp.c #define CHIP_6201 #include <c6x.h> #include <csl.h> #include <csl_irq.h> #include <csl_dma.h> #include <csl_mcbsp.h> #define BUFFER_SIZE 256 int recv0_done = 0; int xmit0_done = 0; unsigned int wait = 0; static Uint32 dmaInbuff[BUFFER_SIZE]; static Uint32 dmaOutbuff[BUFFER_SIZE]; MCBSP_Handle hMcbsp0; DMA_Handle hDma0; DMA_Handle hDma1; void init_mcbsp0(void); void set_interrupts(void); void init_dma0(void); void init_dma1(void); interrupt void nmiIsr(void); interrupt void int4Isr(void); interrupt void int5Isr(void); interrupt void int6Isr(void); interrupt void int7Isr(void); interrupt void int8Isr(void); interrupt void int9Isr(void); interrupt void int10Isr(void); interrupt void int11Isr(void); interrupt void int12Isr(void); interrupt void int13Isr(void); interrupt void int14Isr(void); interrupt void int15Isr(void); void main(void) { IRQ_setVecs((void*)0x03000000); CSL_init(); IRQ_resetAll(); init_mcbsp0(); MCBSP_enableSrgr(hMcbsp0); for(wait=0; wait<20; wait++); // Wait 2 CLKG bit clocks DMA_reset(INV); /* reset all DMA channels */ for (wait=0;wait<BUFFER_SIZE;wait++) { dmaOutbuff[wait]=0x0000000+wait; /* Initialize the transmit buffer */ dmaInbuff[wait]=0; /* Initialize the receive buffer */ } init_dma0(); init_dma1(); set_interrupts(); DMA_start(hDma0); DMA_start(hDma1); MCBSP_enableRcv(hMcbsp0); MCBSP_enableXmt(hMcbsp0); MCBSP_enableFsync(hMcbsp0); /* Wait for interrupt to the CPU when DMA transfer/receive is done */ while (!xmit0_done || !recv0_done); DMA_stop(hDma0); DMA_stop(hDma1); MCBSP_close(hMcbsp0); DMA_close(hDma0); DMA_close(hDma1); } void init_mcbsp0(void) { MCBSP_Config mcbspCfg0 = { MCBSP_SPCR_RMK(MCBSP_SPCR_FRST_YES, MCBSP_SPCR_GRST_YES, MCBSP_SPCR_XINTM_XRDY, MCBSP_SPCR_XRST_YES, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_DISABLE, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_YES), MCBSP_RCR_RMK(MCBSP_RCR_RPHASE_SINGLE, MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_MSB, MCBSP_RCR_RFIG_YES, MCBSP_RCR_RDATDLY_1BIT, MCBSP_RCR_RFRLEN1_OF(0), MCBSP_RCR_RWDLEN1_32BIT), MCBSP_XCR_RMK(MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(63), MCBSP_XCR_XWDLEN2_32BIT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_YES, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XFRLEN1_OF(0), MCBSP_XCR_XWDLEN1_32BIT), MCBSP_SRGR_RMK(MCBSP_SRGR_GSYNC_DEFAULT, MCBSP_SRGR_CLKSP_DEFAULT, MCBSP_SRGR_CLKSM_DEFAULT, MCBSP_SRGR_FSGM_FSG, MCBSP_SRGR_FPER_OF(31), MCBSP_SRGR_FWID_OF(0), MCBSP_SRGR_CLKGDV_OF(7)), MCBSP_MCR_DEFAULT, MCBSP_RCER_DEFAULT, MCBSP_XCER_DEFAULT, MCBSP_PCR_RMK(MCBSP_PCR_XIOEN_SP, MCBSP_PCR_RIOEN_SP, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_EXTERNAL, MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_INPUT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_DEFAULT, MCBSP_PCR_FSRP_DEFAULT, MCBSP_PCR_CLKXP_DEFAULT, MCBSP_PCR_CLKRP_DEFAULT) }; hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp0, &mcbspCfg0); for(wait=0; wait<10; wait++); } void init_dma0(void) { hDma0 = DMA_open(DMA_CHA0, DMA_OPEN_RESET); /* Handle to DMA channel 0 */ DMA_configArgs(hDma0, DMA_PRICTL_RMK(DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, /* TCINT =1 */ DMA_PRICTL_PRI_DMA, /* DMA high priority */ DMA_PRICTL_WSYNC_XEVT0, /* Set synch event */ DMA_PRICTL_RSYNC_DEFAULT, DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, /* Element size */ DMA_PRICTL_DSTDIR_DEFAULT, DMA_PRICTL_SRCDIR_INC, /* Incr by element size */ DMA_PRICTL_START_DEFAULT), DMA_SECCTL_RMK(//DMA_SECCTL_WSPOL_DEFAULT, //DMA_SECCTL_RSPOL_DEFAULT, //DMA_SECCTL_FSIG_DEFAULT, DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, /* Enables DMA intr */ DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT), DMA_SRC_RMK((Uint32)dmaOutbuff), /* Set source to dmaOutbuff */ DMA_DST_RMK(MCBSP_ADDRH(hMcbsp0, DXR)), /* Set dest to DXR */ DMA_XFRCNT_RMK(DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(BUFFER_SIZE))); } void init_dma1(void) { hDma1 = DMA_open(DMA_CHA1, DMA_OPEN_RESET); /* Handle to DMA channel 1 */ DMA_configArgs(hDma1, DMA_PRICTL_RMK(DMA_PRICTL_DSTRLD_DEFAULT, DMA_PRICTL_SRCRLD_DEFAULT, DMA_PRICTL_EMOD_DEFAULT, DMA_PRICTL_FS_DEFAULT, DMA_PRICTL_TCINT_ENABLE, /* TCINT =1 */ DMA_PRICTL_PRI_DMA, /* DMA high priority */ DMA_PRICTL_WSYNC_DEFAULT, DMA_PRICTL_RSYNC_REVT0, /* Set sync event */ DMA_PRICTL_INDEX_DEFAULT, DMA_PRICTL_CNTRLD_DEFAULT, DMA_PRICTL_SPLIT_DEFAULT, DMA_PRICTL_ESIZE_32BIT, /* Element size */ DMA_PRICTL_DSTDIR_INC, /* Incr dest by element */ DMA_PRICTL_SRCDIR_DEFAULT, DMA_PRICTL_START_DEFAULT), DMA_SECCTL_RMK(//DMA_SECCTL_WSPOL_DEFAULT, //DMA_SECCTL_RSPOL_DEFAULT, //DMA_SECCTL_FSIG_DEFAULT, DMA_SECCTL_DMACEN_DEFAULT, DMA_SECCTL_WSYNCCLR_DEFAULT, DMA_SECCTL_WSYNCSTAT_DEFAULT, DMA_SECCTL_RSYNCCLR_DEFAULT, DMA_SECCTL_RSYNCSTAT_DEFAULT, DMA_SECCTL_WDROPIE_DEFAULT, DMA_SECCTL_WDROPCOND_DEFAULT, DMA_SECCTL_RDROPIE_DEFAULT, DMA_SECCTL_RDROPCOND_DEFAULT, DMA_SECCTL_BLOCKIE_ENABLE, /* Enables DMA intr */ DMA_SECCTL_BLOCKCOND_DEFAULT, DMA_SECCTL_LASTIE_DEFAULT, DMA_SECCTL_LASTCOND_DEFAULT, DMA_SECCTL_FRAMEIE_DEFAULT, DMA_SECCTL_FRAMECOND_DEFAULT, DMA_SECCTL_SXIE_DEFAULT, DMA_SECCTL_SXCOND_DEFAULT), DMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)), /* Set source to DRR */ DMA_DST_RMK((Uint32)dmaInbuff), /* Set dest to dmaInbuff */ DMA_XFRCNT_RMK(DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(BUFFER_SIZE))); } void set_interrupts(void) { IRQ_map(IRQ_EVT_DMAINT0, 8); IRQ_enable(IRQ_EVT_DMAINT0); IRQ_map(IRQ_EVT_DMAINT1, 9); IRQ_enable(IRQ_EVT_DMAINT1); IRQ_nmiEnable(); IRQ_globalEnable(); } interrupt void nmiIsr(void) {} interrupt void int4Isr(void) {} interrupt void int5Isr(void) {} interrupt void int6Isr(void) {} interrupt void int7Isr(void) {} interrupt void int8Isr(void) { xmit0_done = 1; } interrupt void int9Isr(void) { recv0_done = 1; } interrupt void int10Isr(void) {} interrupt void int11Isr(void) {} interrupt void int12Isr(void) {} interrupt void int13Isr(void) {} interrupt void int14Isr(void) {} interrupt void int15Isr(void) {} // end of main function file mcbsp_dsp.c // the interrupt service table file vectors.asm .ref _c_int00 .ref _nmiIsr .ref _int4Isr .ref _int5Isr .ref _int6Isr .ref _int7Isr .ref _int8Isr .ref _int9Isr .ref _int10Isr .ref _int11Isr .ref _int12Isr .ref _int13Isr .ref _int14Isr .ref _int15Isr ; Macro Definition ; For unused entries in Int Vector Table unused .macro id .global unused:id: unused:id: b unused:id: nop nop nop nop nop nop nop .endm ; Interrupt Vector Table .sect "vectors" ; Define Memory Section _RESET: mvkl _c_int00, b0 ; Reset Vector mvkh _c_int00, b0 b b0 nop nop nop nop nop _NMI: mvkl _nmiIsr, b0 ; NMI Service Function mvkh _nmiIsr, b0 b b0 nop nop nop nop nop _RESV1: unused RESV1 _RESV2: unused RESV2 _INT4: mvkl _int4Isr, b0 ; INT4 Service Function mvkh _int4Isr, b0 b b0 nop nop nop nop nop _INT5: mvkl _int5Isr, b0 ; INT5 Service Function mvkh _int5Isr, b0 b b0 nop nop nop nop nop _INT6: mvkl _int6Isr, b0 ; INT6 Service Function mvkh _int6Isr, b0 b b0 nop nop nop nop nop _INT7: mvkl _int7Isr, b0 ; INT7 Service Function mvkh _int7Isr, b0 b b0 nop nop nop nop nop _INT8: mvkl _int8Isr, b0 ; INT8 Service Function mvkh _int8Isr, b0 b b0 nop nop nop nop nop _INT9: mvkl _int9Isr, b0 ; INT9 Service Function mvkh _int9Isr, b0 b b0 nop nop nop nop nop _INT10: mvkl _int10Isr, b0 ; INT10 Service Function mvkh _int10Isr, b0 b b0 nop nop nop nop nop _INT11: mvkl _int11Isr, b0 ; INT11 Service Function mvkh _int11Isr, b0 b b0 nop nop nop nop nop _INT12: mvkl _int12Isr, b0 ; INT12 Service Function mvkh _int12Isr, b0 b b0 nop nop nop nop nop _INT13: mvkl _int13Isr, b0 ; INT13 Service Function mvkh _int13Isr, b0 b b0 nop nop nop nop nop _INT14: mvkl _int14Isr, b0 ; INT14 Service Function mvkh _int14Isr, b0 b b0 nop nop nop nop nop _INT15: mvkl _int15Isr, b0 ; INT15 Service Function mvkh _int15Isr, b0 b b0 nop nop nop nop nop .end // end of the interrupt service table file vectors.asm // the command file 4290.cmd MEMORY { IDRAM0 (RWI) : org = 0x80000000, len = 0x00008000 IDRAM1 (RWI) : org = 0x80008000, len = 0x00008000 IPRAM (RWIX) : org = 0x01400000, len = 0x00010000 GRAM (RWIX) : org = 0x0000c400, len = 0x001f3bff SDRAM (RWIX) : org = 0x02020800, len = 0x00FaF800 SBSRAM0 (RWIX): org = 0x03000000, len = 0x00000200 SBSRAM (RWIX) : org = 0x03000200, len = 0x0007FE00 } SECTIONS { vectors : > SBSRAM0 .buffer0 : > IDRAM0 .buffer1 : > IDRAM1 .buffer2 : > SDRAM .globaldata : > IDRAM0 .stack : > IDRAM1 .text : > SBSRAM .ptext : > SBSRAM .cinit : > SBSRAM .const : > SBSRAM .switch : > SBSRAM .data : > SBSRAM .bss : > SBSRAM .cio : > SBSRAM .sysmem : > SBSRAM .far : > SBSRAM .xref : > SBSRAM } // end of command file 4290.cmd Wang Tao -- |