PLL with external feedback at 622.08

Started by January 5, 2009
Hi All
I�m going to design a PLL for the frequency of 622.08MHz. This PLL
should support external feedback. I�ve looked for such PLL muck but I
haven�t found .
What shall I do if such a PLL doesn�t exist?
I know that there is many �phase and freq. detector� and
VCXO from
different vendors but I don�t know how to design Loop filter and
charge pump.
Is there any IC that integrates phase-frequency detector, loop filter
and charge pump?
 I�ll very appreciate anyone who helps me.
On Jan 6, 4:59�am, sungja...@gmail.com wrote:
> Hi All > I�m going to design a PLL for the frequency of 622.08MHz. This PLL > should support external feedback. I�ve looked for such PLL muck but I > haven�t found . > What shall I do if such a PLL doesn�t exist? > I know that there is many �phase and freq. detector� and
VCXO from
> different vendors but I don�t know how to design Loop filter and > charge pump. > Is there any IC that integrates phase-frequency detector, loop filter > and charge pump? > �I�ll very appreciate anyone who helps me.
Is this to be an analogue PLL? You can use a multiplier for the phase detector and a VCO (square-wave) for the free-running oscillator. I would suggest you buy an IC if possible though. H.
On Jan 6, 4:59�am, sungja...@gmail.com wrote:
> Hi All > I�m going to design a PLL for the frequency of 622.08MHz. This PLL > should support external feedback. I�ve looked for such PLL muck but I > haven�t found . > What shall I do if such a PLL doesn�t exist? > I know that there is many �phase and freq. detector� and
VCXO from
> different vendors but I don�t know how to design Loop filter and > charge pump. > Is there any IC that integrates phase-frequency detector, loop filter > and charge pump? > �I�ll very appreciate anyone who helps me.
Forgot to add - you will need the Bode plot (open-loop) of your PLL. The VCO is an integrator k/s and the multiplier can be approximated for small swings in phase to be a summing junction (+/-). You will need a filter which makes you a half-decent phase- margin. However, your free-running freq is 622.08MHz which will give rise to a freq of twice this value ie over 1 GHz! This frequency must be filtered by the loop and you must decide on a suitable unity-gain crossover frequency. I suggest 2Fc/10 which is around 120MHz. Swot up on your undergrad control theory! H.
sungjack0@gmail.com wrote in news:1330d8d5-bf1e-48a7-aeab-b1d127344397
@a26g2000prf.googlegroups.com:

> Hi All > I�m going to design a PLL for the frequency of 622.08MHz. This PLL > should support external feedback. I�ve looked for such PLL muck but I > haven�t found . > What shall I do if such a PLL doesn�t exist? > I know that there is many �phase and freq. detector� and
VCXO from
> different vendors but I don�t know how to design Loop filter and > charge pump. > Is there any IC that integrates phase-frequency detector, loop filter > and charge pump? > I�ll very appreciate anyone who helps me.
There are plenty of PLL chips out there that can do this. I know, 'cause I've done PLLs out of discrete parts at 622.08MHz in a couple of designs. Note that the PFD probably won't see the 622.08MHz signals, as you'll need to work at a much lower frequency to keep the gain low enough to put the loop bw where you want it (I'm guessing this will be << 10kHz). They aren't too hard to get working first time either; the models are good and everything can be simulated or analysed, with a good match between simulation and reality. (Actually, the best way to get a good design is to synthesise one from the requirements. There are too many variables in too many dimensions to be able to "design" by some empirical adjustment method. Simulation is just used to verify the design, not to "tune" it.) However, that's me. I really suggest you go for a canned solution to increase your chance of success. (I'm not trying to boast here, just point out that PLL design is non- trivial for the beginner. I have yet to find a good book on PLLs that actually tells you the things you need to know to make a design that works well in the real world. The basic problem seems to be that most PLL books or app notes are written by people who assume their readers are designing radios, not SONET/SDH systems. Many of the concepts presented are just plain wrong.) Examples of canned solutions would be the parts on this page: http://www.zarlink.com/zarlink/hs/timing.htm Don't forget these requirements: - What amount of intrinsic jitter are you allowed to generate? (Hint: Read G.783 section 9.3) - What amount of input jitter must your design tolerate? (Hint: Read G.825) - What JTF mask applies? (Hint: Read GR253 R5-239) - Does you design have to switch between inputs? This is sometimes done when an input (clock) fails. There are numerous specifications regarding how much jitter your design can generate during such operations. Regards, Allan