Oversampling in an ADC to improve performance

Started by Jorge Rivas January 6, 2010
Hi all,

I have a communications system that is streaming analog data. On the
receiver side, this data is converted by an ADC with an oversampling of
4 related to the conversion rate of the DAC on the transmitter. As it is
a system under testing (with variable speed), we don't have a proper
steep analog filter before the ADC, so the oversampling will help to
achieve a better performance. In my receiver (a custom FPGA board), the
ADC gives 4 different streams (synchronized) with the interpolated data.

The problem with this interpolated data is that the symbol rate
increases, so there is too many samples for the rest of the receiver. I
know I could discard 3 of the 4 streams and I would have the sent data
rate (fixing so many other troubles :D), but then the oversampling made
would be useless.

Another option would be to downsample the samples directly inside the
FPGA, but this would give the same result as in the previous paragraph.
Which is the proper way to handle that high number of samples?

Thanks in advance :)


Homework?

Jorge Rivas wrote:

> Hi all, > > I have a communications system that is streaming analog data. On the > receiver side, this data is converted by an ADC with an oversampling of > 4 related to the conversion rate of the DAC on the transmitter. As it is > a system under testing (with variable speed), we don't have a proper > steep analog filter before the ADC, so the oversampling will help to > achieve a better performance. In my receiver (a custom FPGA board), the > ADC gives 4 different streams (synchronized) with the interpolated data. > > The problem with this interpolated data is that the symbol rate > increases, so there is too many samples for the rest of the receiver. I > know I could discard 3 of the 4 streams and I would have the sent data > rate (fixing so many other troubles :D), but then the oversampling made > would be useless. > > Another option would be to downsample the samples directly inside the > FPGA, but this would give the same result as in the previous paragraph. > Which is the proper way to handle that high number of samples? > > Thanks in advance :)
On Jan 6, 12:33=A0pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl>
wrote:
> Hi all, > > I have a communications system that is streaming analog data. On the > receiver side, this data is converted by an ADC with an oversampling of > 4 related to the conversion rate of the DAC on the transmitter. As it is > a system under testing (with variable speed), we don't have a proper > steep analog filter before the ADC, so the oversampling will help to > achieve a better performance. In my receiver (a custom FPGA board), the > ADC gives 4 different streams (synchronized) with the interpolated data. > > The problem with this interpolated data is that the symbol rate > increases, so there is too many samples for the rest of the receiver. I > know I could discard 3 of the 4 streams and I would have the sent data > rate (fixing so many other troubles :D), but then the oversampling made > would be useless. > > Another option would be to downsample the samples directly inside the > FPGA, but this would give the same result as in the previous paragraph. > Which is the proper way to handle that high number of samples? > > Thanks in advance :)
I am not clear about some of your terminology, but I think you are describing a receiver that is oversampling a bandlimited signal. It does not matter what the rate of the DAC is at the transmitter, only the frequency and bandwidth of the signal being sent. You don't say what your signal frequency is, but I assume it is baseband at this point. So if you oversample, you can discard samples simply. But that tosses out all the advantage of oversampling in the first place. To retain the advantages, you need to use a digital low pass filter before decimating. In fact, if you use a FIR filter, you can gain some computational efficiency by omitting the calculations of the the discarded samples. If your signal is at a frequency higher than your nyquist rate, you need to consider the frequency downconversion that will happen as you decimate. If this does not put your signal at baseband where you need it, then you must use a digital mixer to achieve the final result, either by mixing before the downconversion or before. Mixing after the downconversion allows you to combine the input low pass filter with the down conversion as described above. Do I understand what you are trying to do or have I muffed it? Rick
On 1/6/2010 6:51 PM, ralphmalph wrote:
> On Jan 6, 12:33 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> > wrote: >> Hi all, >> >> I have a communications system that is streaming analog data. On the >> receiver side, this data is converted by an ADC with an oversampling of >> 4 related to the conversion rate of the DAC on the transmitter. As it is >> a system under testing (with variable speed), we don't have a proper >> steep analog filter before the ADC, so the oversampling will help to >> achieve a better performance. In my receiver (a custom FPGA board), the >> ADC gives 4 different streams (synchronized) with the interpolated data. >> >> The problem with this interpolated data is that the symbol rate >> increases, so there is too many samples for the rest of the receiver. I >> know I could discard 3 of the 4 streams and I would have the sent data >> rate (fixing so many other troubles :D), but then the oversampling made >> would be useless. >> >> Another option would be to downsample the samples directly inside the >> FPGA, but this would give the same result as in the previous paragraph. >> Which is the proper way to handle that high number of samples? >> >> Thanks in advance :) > > I am not clear about some of your terminology, but I think you are > describing a receiver that is oversampling a bandlimited signal. It > does not matter what the rate of the DAC is at the transmitter, only > the frequency and bandwidth of the signal being sent. > > You don't say what your signal frequency is, but I assume it is > baseband at this point. So if you oversample, you can discard samples > simply. But that tosses out all the advantage of oversampling in the > first place. To retain the advantages, you need to use a digital low > pass filter before decimating. In fact, if you use a FIR filter, you > can gain some computational efficiency by omitting the calculations of > the the discarded samples. > > If your signal is at a frequency higher than your nyquist rate, you > need to consider the frequency downconversion that will happen as you > decimate. If this does not put your signal at baseband where you need > it, then you must use a digital mixer to achieve the final result, > either by mixing before the downconversion or before. Mixing after > the downconversion allows you to combine the input low pass filter > with the down conversion as described above. > > Do I understand what you are trying to do or have I muffed it? > > Rick
Thanks for your reply, Rick. The transmitted signal is indeed baseband. The spectrum of the signal is pretty flat and has a bandwidth of around 300 MHz. The DAC is sampling at 600 MSPS. I cannot use a digital low pass filter directly on the input streaming, because the clock frequency would be too high for my FPGA. There is another problem, though. Each one of the streams of interpolated data that go into the FPGA are already parallelized and do not correspond directly with the sampled data. The ADC gives 8 bits of resolution per sample, but on the FPGA I receive 4 streams of 32-bit wide symbols each. I can understand what happens when a signal is interpolated or decimated, but I ran out of ideas quite fast when there are Serial to Parallel converters in the middle. The only thing I can think of is bit manipulation... Any idea?
On Jan 6, 1:49=A0pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> wrote:
> On 1/6/2010 6:51 PM, ralphmalph wrote: > > > > > On Jan 6, 12:33 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> > > wrote: > >> Hi all, > > >> I have a communications system that is streaming analog data. On the > >> receiver side, this data is converted by an ADC with an oversampling o=
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> >> 4 related to the conversion rate of the DAC on the transmitter. As it =
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> >> a system under testing (with variable speed), we don't have a proper > >> steep analog filter before the ADC, so the oversampling will help to > >> achieve a better performance. In my receiver (a custom FPGA board), th=
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> >> ADC gives 4 different streams (synchronized) with the interpolated dat=
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> > >> The problem with this interpolated data is that the symbol rate > >> increases, so there is too many samples for the rest of the receiver. =
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> >> know I could discard 3 of the 4 streams and I would have the sent data > >> rate (fixing so many other troubles :D), but then the oversampling mad=
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> >> would be useless. > > >> Another option would be to downsample the samples directly inside the > >> FPGA, but this would give the same result as in the previous paragraph=
.
> >> Which is the proper way to handle that high number of samples? > > >> Thanks in advance :) > > > I am not clear about some of your terminology, but I think you are > > describing a receiver that is oversampling a bandlimited signal. =A0It > > does not matter what the rate of the DAC is at the transmitter, only > > the frequency and bandwidth of the signal being sent. > > > You don't say what your signal frequency is, but I assume it is > > baseband at this point. =A0So if you oversample, you can discard sample=
s
> > simply. =A0But that tosses out all the advantage of oversampling in the > > first place. =A0To retain the advantages, you need to use a digital low > > pass filter before decimating. =A0In fact, if you use a FIR filter, you > > can gain some computational efficiency by omitting the calculations of > > the the discarded samples. > > > If your signal is at a frequency higher than your nyquist rate, you > > need to consider the frequency downconversion that will happen as you > > decimate. =A0If this does not put your signal at baseband where you nee=
d
> > it, then you must use a digital mixer to achieve the final result, > > either by mixing before the downconversion or before. =A0Mixing after > > the downconversion allows you to combine the input low pass filter > > with the down conversion as described above. > > > Do I understand what you are trying to do or have I muffed it? > > > Rick > > Thanks for your reply, Rick. > > The transmitted signal is indeed baseband. The spectrum of the signal is > pretty flat and has a bandwidth of around 300 MHz. The DAC is sampling > at 600 MSPS. > > I cannot use a digital low pass filter directly on the input streaming, > because the clock frequency would be too high for my FPGA. There is > another problem, though. Each one of the streams of interpolated data > that go into the FPGA are already parallelized and do not correspond > directly with the sampled data. The ADC gives 8 bits of resolution per > sample, but on the FPGA I receive 4 streams of 32-bit wide symbols each. > > I can understand what happens when a signal is interpolated or > decimated, but I ran out of ideas quite fast when there are Serial to > Parallel converters in the middle. The only thing I can think of is bit > manipulation... Any idea?
From your description, the FPGA receives rate 4X ADC data in blocks of 16 8-bit samples. You want to decimate the rate to X. A crude decimator with sinx/x response would add four sets of four time- sequential 8-bit samples in each block of 16 together: 16 samples in, 4 samples out. John
Jorge Rivas wrote:
> Hi all, > > I have a communications system that is streaming analog data. On the > receiver side, this data is converted by an ADC with an oversampling of > 4 related to the conversion rate of the DAC on the transmitter. As it is > a system under testing (with variable speed), we don't have a proper > steep analog filter before the ADC, so the oversampling will help to > achieve a better performance. In my receiver (a custom FPGA board), the > ADC gives 4 different streams (synchronized) with the interpolated data. > > The problem with this interpolated data is that the symbol rate > increases, so there is too many samples for the rest of the receiver. I > know I could discard 3 of the 4 streams and I would have the sent data > rate (fixing so many other troubles :D), but then the oversampling made > would be useless. > > Another option would be to downsample the samples directly inside the > FPGA, but this would give the same result as in the previous paragraph. > Which is the proper way to handle that high number of samples? > > Thanks in advance :) > >
You need to do a proper link budget. I don't see one here. And I don't see how you do 3 or 4 streams with "an" DAC. Seriously, hire a proper systems engineer and get all this sorted out. -- Les Cargill
On 1/7/2010 12:03 AM, John wrote:
> On Jan 6, 1:49 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> wrote: >> On 1/6/2010 6:51 PM, ralphmalph wrote: >> >> >> >>> On Jan 6, 12:33 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> >>> wrote: >>>> Hi all, >> >>>> I have a communications system that is streaming analog data. On the >>>> receiver side, this data is converted by an ADC with an oversampling of >>>> 4 related to the conversion rate of the DAC on the transmitter. As it is >>>> a system under testing (with variable speed), we don't have a proper >>>> steep analog filter before the ADC, so the oversampling will help to >>>> achieve a better performance. In my receiver (a custom FPGA board), the >>>> ADC gives 4 different streams (synchronized) with the interpolated data. >> >>>> The problem with this interpolated data is that the symbol rate >>>> increases, so there is too many samples for the rest of the receiver. I >>>> know I could discard 3 of the 4 streams and I would have the sent data >>>> rate (fixing so many other troubles :D), but then the oversampling made >>>> would be useless. >> >>>> Another option would be to downsample the samples directly inside the >>>> FPGA, but this would give the same result as in the previous paragraph. >>>> Which is the proper way to handle that high number of samples? >> >>>> Thanks in advance :) >> >>> I am not clear about some of your terminology, but I think you are >>> describing a receiver that is oversampling a bandlimited signal. It >>> does not matter what the rate of the DAC is at the transmitter, only >>> the frequency and bandwidth of the signal being sent. >> >>> You don't say what your signal frequency is, but I assume it is >>> baseband at this point. So if you oversample, you can discard samples >>> simply. But that tosses out all the advantage of oversampling in the >>> first place. To retain the advantages, you need to use a digital low >>> pass filter before decimating. In fact, if you use a FIR filter, you >>> can gain some computational efficiency by omitting the calculations of >>> the the discarded samples. >> >>> If your signal is at a frequency higher than your nyquist rate, you >>> need to consider the frequency downconversion that will happen as you >>> decimate. If this does not put your signal at baseband where you need >>> it, then you must use a digital mixer to achieve the final result, >>> either by mixing before the downconversion or before. Mixing after >>> the downconversion allows you to combine the input low pass filter >>> with the down conversion as described above. >> >>> Do I understand what you are trying to do or have I muffed it? >> >>> Rick >> >> Thanks for your reply, Rick. >> >> The transmitted signal is indeed baseband. The spectrum of the signal is >> pretty flat and has a bandwidth of around 300 MHz. The DAC is sampling >> at 600 MSPS. >> >> I cannot use a digital low pass filter directly on the input streaming, >> because the clock frequency would be too high for my FPGA. There is >> another problem, though. Each one of the streams of interpolated data >> that go into the FPGA are already parallelized and do not correspond >> directly with the sampled data. The ADC gives 8 bits of resolution per >> sample, but on the FPGA I receive 4 streams of 32-bit wide symbols each. >> >> I can understand what happens when a signal is interpolated or >> decimated, but I ran out of ideas quite fast when there are Serial to >> Parallel converters in the middle. The only thing I can think of is bit >> manipulation... Any idea? > > From your description, the FPGA receives rate 4X ADC data in blocks of > 16 8-bit samples. You want to decimate the rate to X. A crude > decimator with sinx/x response would add four sets of four time- > sequential 8-bit samples in each block of 16 together: 16 samples in, > 4 samples out. > > John
Hi John, That is exactly what I need, but I don't think I understand your answer completely. I think you mean that I should have a 4-input decimator and introduce on each input the 1st, 2nd, 3rd and 4th "part" of my received block on the FPGA, being each of those parts respectively the 1st, 2nd, 3rd and 4th part of the received time-sequence time on the ADC before the parallel conversion, am I right? Thanks a lot for your answer, Jorge
On 1/7/2010 2:44 AM, Les Cargill wrote:
> Jorge Rivas wrote: >> Hi all, >> >> I have a communications system that is streaming analog data. On the >> receiver side, this data is converted by an ADC with an oversampling of >> 4 related to the conversion rate of the DAC on the transmitter. As it is >> a system under testing (with variable speed), we don't have a proper >> steep analog filter before the ADC, so the oversampling will help to >> achieve a better performance. In my receiver (a custom FPGA board), the >> ADC gives 4 different streams (synchronized) with the interpolated data. >> >> The problem with this interpolated data is that the symbol rate >> increases, so there is too many samples for the rest of the receiver. I >> know I could discard 3 of the 4 streams and I would have the sent data >> rate (fixing so many other troubles :D), but then the oversampling made >> would be useless. >> >> Another option would be to downsample the samples directly inside the >> FPGA, but this would give the same result as in the previous paragraph. >> Which is the proper way to handle that high number of samples? >> >> Thanks in advance :) >> >> > > > You need to do a proper link budget. I don't see one here. And I don't > see how you do 3 or 4 streams with "an" DAC. > > Seriously, hire a proper systems engineer and get all this > sorted out. > > -- > Les Cargill > >
Hi Les, The link budget is not an issue right now. The 4 streams correspond to the outputs of an *ADC* working at a higher frequency than the rest of the system. Jorge
Jorge Rivas wrote:
> On 1/7/2010 2:44 AM, Les Cargill wrote: >> Jorge Rivas wrote: >>> Hi all, >>> >>> I have a communications system that is streaming analog data. On the >>> receiver side, this data is converted by an ADC with an oversampling of >>> 4 related to the conversion rate of the DAC on the transmitter. As it is >>> a system under testing (with variable speed), we don't have a proper >>> steep analog filter before the ADC, so the oversampling will help to >>> achieve a better performance. In my receiver (a custom FPGA board), the >>> ADC gives 4 different streams (synchronized) with the interpolated data. >>> >>> The problem with this interpolated data is that the symbol rate >>> increases, so there is too many samples for the rest of the receiver. I >>> know I could discard 3 of the 4 streams and I would have the sent data >>> rate (fixing so many other troubles :D), but then the oversampling made >>> would be useless. >>> >>> Another option would be to downsample the samples directly inside the >>> FPGA, but this would give the same result as in the previous paragraph. >>> Which is the proper way to handle that high number of samples? >>> >>> Thanks in advance :) >>> >>> >> >> You need to do a proper link budget. I don't see one here. And I don't >> see how you do 3 or 4 streams with "an" DAC. >> >> Seriously, hire a proper systems engineer and get all this >> sorted out. >> >> -- >> Les Cargill >> >> > > Hi Les, > > The link budget is not an issue right now. The 4 streams correspond to > the outputs of an *ADC* working at a higher frequency than the rest of > the system. > > Jorge
My bad - others mentioned decimation. I did not mean the RF link budget, but the bitrates of the various blocks in the digital domain. Poor choice of words on my part. -- Les Cargill
On Jan 6, 1:49 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> wrote:
> On 1/6/2010 6:51 PM, ralphmalph wrote: > > > > > On Jan 6, 12:33 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> > > wrote: > >> Hi all, > > >> I have a communications system that is streaming analog data. On the > >> receiver side, this data is converted by an ADC with an oversampling of > >> 4 related to the conversion rate of the DAC on the transmitter. As it is > >> a system under testing (with variable speed), we don't have a proper > >> steep analog filter before the ADC, so the oversampling will help to > >> achieve a better performance. In my receiver (a custom FPGA board), the > >> ADC gives 4 different streams (synchronized) with the interpolated data. > > >> The problem with this interpolated data is that the symbol rate > >> increases, so there is too many samples for the rest of the receiver. I > >> know I could discard 3 of the 4 streams and I would have the sent data > >> rate (fixing so many other troubles :D), but then the oversampling made > >> would be useless. > > >> Another option would be to downsample the samples directly inside the > >> FPGA, but this would give the same result as in the previous paragraph. > >> Which is the proper way to handle that high number of samples? > > >> Thanks in advance :) > > > I am not clear about some of your terminology, but I think you are > > describing a receiver that is oversampling a bandlimited signal. It > > does not matter what the rate of the DAC is at the transmitter, only > > the frequency and bandwidth of the signal being sent. > > > You don't say what your signal frequency is, but I assume it is > > baseband at this point. So if you oversample, you can discard samples > > simply. But that tosses out all the advantage of oversampling in the > > first place. To retain the advantages, you need to use a digital low > > pass filter before decimating. In fact, if you use a FIR filter, you > > can gain some computational efficiency by omitting the calculations of > > the the discarded samples. > > > If your signal is at a frequency higher than your nyquist rate, you > > need to consider the frequency downconversion that will happen as you > > decimate. If this does not put your signal at baseband where you need > > it, then you must use a digital mixer to achieve the final result, > > either by mixing before the downconversion or before. Mixing after > > the downconversion allows you to combine the input low pass filter > > with the down conversion as described above. > > > Do I understand what you are trying to do or have I muffed it? > > > Rick > > Thanks for your reply, Rick. > > The transmitted signal is indeed baseband. The spectrum of the signal is > pretty flat and has a bandwidth of around 300 MHz. The DAC is sampling > at 600 MSPS.
Is this a typo? If your signal has a 300 MHz bandwidth, then you must sample it at a minimum of 600 MSPS to accurately represent it discretely. I understand that the DAC is creating the signal, but are you saying that the ADC is sampling at 2400 MSPS??? That is pretty durn fast!
> I cannot use a digital low pass filter directly on the input streaming, > because the clock frequency would be too high for my FPGA. There is > another problem, though. Each one of the streams of interpolated data > that go into the FPGA are already parallelized and do not correspond > directly with the sampled data. The ADC gives 8 bits of resolution per > sample, but on the FPGA I receive 4 streams of 32-bit wide symbols each.
Ok, if you don't want to filter the ADC data before you decimate it, you can toss samples without filtering, but you will not gain any advantage from the higher sample rate. What you say about the data being "parallelized" and not corresponding to the sampled data makes no sense to me. The way the data is bundled at the input to the FPGA is not material except that you must sort it out inside the FPGA so that you have a sequential data stream. If you are interleaving multiple ADCs to increase the sample rate, you just have to interleave the input data to match. That would use a mux.
> I can understand what happens when a signal is interpolated or > decimated, but I ran out of ideas quite fast when there are Serial to > Parallel converters in the middle. The only thing I can think of is bit > manipulation... Any idea?
I think you are confusing yourself. Whether the data is serial or parallel is irrelevant to this exercise. Data is data. The only concern is that you keep the order of the samples consistent. Your initial post seems to accurately describe your situation. You can decimate without filtering and get nothing from the oversampling or you can use a digital filter before decimating which effectively averages the multiple samples to improve the S/N ratio. So what exactly are you not clear on? Rick