Jim Thompson wrote:> On Sat, 13 Oct 2012 07:23:37 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > > >On 10/12/2012 12:42 PM, Jim Thompson wrote: > >> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold > >> <gherold@teachspin.com> wrote: > >> > >>> On Oct 11, 4:36 pm, Tim Wescott<t...@seemywebsite.com> wrote: > >>>> How commonly do you see PLL designs referred to as "type I", "type II", > >>>> "type III", etc.? Do the terms make sense to you? > >>>> > >>>> I'm writing a report; don't want to either baffle with bullshit nor leave > >>>> out handy terms... > >>>> > >>>> -- > >>>> My liberal friends think I'm a conservative kook. > >>>> My conservative friends think I'm a liberal kook. > >>>> Why am I not happy that they have found common ground? > >>>> > >>>> Tim Wescott, Communications, Control, Circuits& Softwarehttp://www.wescottdesign.com > >>> > >>> Nice thread, thanks Tim. > >>> > >>> I assume "Phaselock Techniques" by Flyod M. Gardener is the right > >>> book. (Making my Xmas wish list.) Any advantage of the third edition > >>> over the second? > >>> > >>> So in a type III system the error signal is integrated twice? > >>> Does anyone have an example where double integration is used? > >>> It doesn't have to be a PLL application any type of control loop would > >>> be fine. > >>> > >>> George H. > >> > >> The extra filter/integrator is usually placed above the zero dB > >> cross-over, just to reduce noise. > >> > >> ...Jim Thompson > > > >No, it's another lead-lag integrator, to reduce the static phase offset > >due to a frequency ramp to zero. Back in the all-analogue days, that > >sometimes mattered. > > > >Cheers > > > >Phil Hobbs > > In _modern_ times. I've not heard that before and I'm wa-a-a-ay older > than you. Analog phase detectors locked at 90�. Although you seem > actually to be implying more loop gain??Yes, third order loops (or type III to salve Tim's wounded control-guy feelings) really use three integrators in the loop, on purpose. If you put a linear ramp into a control system like that, the DC error is zero. Of course it's as squirrelly as can be when it's coming into lock, which is why you need a bunch of analogue switches and so forth to make it work right. Getting that right is such a pain, and so vulnerable to unforeseen circumstances, that it's far, far easier to estimate the ramp rate in software and put some small DC offset on the PD output to compensate. Cheers Phil Hobbs
PLL Terminology Question
Started by ●October 11, 2012
Reply by ●October 13, 20122012-10-13
Reply by ●October 13, 20122012-10-13
John Larkin wrote:> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold > <gherold@teachspin.com> wrote: > > >On Oct 11, 4:36 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> How commonly do you see PLL designs referred to as "type I", "type II", > >> "type III", etc.? Do the terms make sense to you? > >> > >> I'm writing a report; don't want to either baffle with bullshit nor leave > >> out handy terms... > >> > >> -- > >> My liberal friends think I'm a conservative kook. > >> My conservative friends think I'm a liberal kook. > >> Why am I not happy that they have found common ground? > >> > >> Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com > > > >Nice thread, thanks Tim. > > > >I assume "Phaselock Techniques" by Flyod M. Gardener is the right > >book. (Making my Xmas wish list.) Any advantage of the third edition > >over the second? > > > >So in a type III system the error signal is integrated twice? > >Does anyone have an example where double integration is used? > >It doesn't have to be a PLL application any type of control loop would > >be fine. > > > >George H. > > I am a fan of the D-flop bang-bang phase detector. It has, in theory, > an infinite phase-error gain, which makes it interesting to analyze. > That's the way to go if you want to lock an oscillator to an external > input with picosecond long-term stability.The metastability problem is for real, though. Many moons ago (actually in the same DBS system I mentioned in the H parameters thread) I used a 75S74 as a frequency mixer in an offset loop to generate the pilot tones for the satellite uplink. Even with very clean input signals, when I looked at the d-flop output on a spectrum analyzer, the peak looked like one of those old-fashioned drinking fountains that ran all the time--it wobbled and bounced all over, especially at low modulation frequency. I'm really surprised that you can get good stability out of something that ugly. Or has the metastability issue somehow gone away since 1982? Cheers Phil Hobbs
Reply by ●October 13, 20122012-10-13
On Sat, 13 Oct 2012 17:52:57 -0400, Phil Hobbs <pcdhobbsSpamMeSenseless@electrooptical.net> wrote:>John Larkin wrote: > >> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold >> <gherold@teachspin.com> wrote: >> >> >On Oct 11, 4:36 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> >> How commonly do you see PLL designs referred to as "type I", "type II", >> >> "type III", etc.? Do the terms make sense to you? >> >> >> >> I'm writing a report; don't want to either baffle with bullshit nor leave >> >> out handy terms... >> >> >> >> -- >> >> My liberal friends think I'm a conservative kook. >> >> My conservative friends think I'm a liberal kook. >> >> Why am I not happy that they have found common ground? >> >> >> >> Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com >> > >> >Nice thread, thanks Tim. >> > >> >I assume "Phaselock Techniques" by Flyod M. Gardener is the right >> >book. (Making my Xmas wish list.) Any advantage of the third edition >> >over the second? >> > >> >So in a type III system the error signal is integrated twice? >> >Does anyone have an example where double integration is used? >> >It doesn't have to be a PLL application any type of control loop would >> >be fine. >> > >> >George H. >> >> I am a fan of the D-flop bang-bang phase detector. It has, in theory, >> an infinite phase-error gain, which makes it interesting to analyze. >> That's the way to go if you want to lock an oscillator to an external >> input with picosecond long-term stability. > >The metastability problem is for real, though. Many moons ago (actually in the same DBS >system I mentioned in the H parameters thread) I used a 75S74 as a frequency mixer in an >offset loop to generate the pilot tones for the satellite uplink. Even with very clean >input signals, when I looked at the d-flop output on a spectrum analyzer, the peak looked >like one of those old-fashioned drinking fountains that ran all the time--it wobbled and >bounced all over, especially at low modulation frequency. > >I'm really surprised that you can get good stability out of something that ugly. Or has the >metastability issue somehow gone away since 1982? > >Cheers > >Phil HobbsI don't even remember 1982! I used an EclipsLite flop as the bang-bang phase detector in the NIF timing system, differential ECL data and clock at 155.52 MHz, VCXO. Loop bandwidth was something like 10 KHz in search mode, 1 KHz operating, so if there was the occasional metastability, I didn't notice it. We got a couple of ps RMS jitter out of our whole box, so the PLL must have been better. Holding 1 ps out of 6 ns, longterm, is asking a lot of the analog stability of any phase detector, and of the opamps and stuff downstream. TTL logic, with symmetric master-slave flops, tends to dither a lot. Its metastability mode tends to be oscillatory, which essentially clips the positive-feedback loop gain and generally confuses the poor thing. ECL and CMOS gates are more likely to just resolve a little slower. 74LS74s could oscillate for tens of cycles if you teased them just right. Candidate for worst logic family ever, after RTL. Gotta finish fixing the roof. The rainy season is almost here. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Reply by ●October 13, 20122012-10-13
On Sat, 13 Oct 2012 17:52:57 -0400, Phil Hobbs <pcdhobbsSpamMeSenseless@electrooptical.net> wrote:>John Larkin wrote: > >> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold >> <gherold@teachspin.com> wrote: >> >> >On Oct 11, 4:36 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> >> How commonly do you see PLL designs referred to as "type I", "type II", >> >> "type III", etc.? Do the terms make sense to you? >> >> >> >> I'm writing a report; don't want to either baffle with bullshit nor leave >> >> out handy terms... >> >> >> >> -- >> >> My liberal friends think I'm a conservative kook. >> >> My conservative friends think I'm a liberal kook. >> >> Why am I not happy that they have found common ground? >> >> >> >> Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com >> > >> >Nice thread, thanks Tim. >> > >> >I assume "Phaselock Techniques" by Flyod M. Gardener is the right >> >book. (Making my Xmas wish list.) Any advantage of the third edition >> >over the second? >> > >> >So in a type III system the error signal is integrated twice? >> >Does anyone have an example where double integration is used? >> >It doesn't have to be a PLL application any type of control loop would >> >be fine. >> > >> >George H. >> >> I am a fan of the D-flop bang-bang phase detector. It has, in theory, >> an infinite phase-error gain, which makes it interesting to analyze. >> That's the way to go if you want to lock an oscillator to an external >> input with picosecond long-term stability. > >The metastability problem is for real, though. Many moons ago (actually in the same DBS >system I mentioned in the H parameters thread) I used a 75S74 as a frequency mixer in an >offset loop to generate the pilot tones for the satellite uplink. Even with very clean >input signals, when I looked at the d-flop output on a spectrum analyzer, the peak looked >like one of those old-fashioned drinking fountains that ran all the time--it wobbled and >bounced all over, especially at low modulation frequency. > >I'm really surprised that you can get good stability out of something that ugly. Or has the >metastability issue somehow gone away since 1982? > >Cheers > >Phil HobbsA D-flop, by itself, is only good with a VCO that's constrained to less than 2:1 tuning range. Otherwise you can get harmonic locking... not necessarily bad, I've used it to advantage... see my patents. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●October 13, 20122012-10-13
Jim Thompson wrote:> > On Sat, 13 Oct 2012 17:52:57 -0400, Phil Hobbs > <pcdhobbsSpamMeSenseless@electrooptical.net> wrote: > > >John Larkin wrote: > > > >> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold > >> <gherold@teachspin.com> wrote: > >> > >> >On Oct 11, 4:36 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> >> How commonly do you see PLL designs referred to as "type I", "type II", > >> >> "type III", etc.? Do the terms make sense to you? > >> >> > >> >> I'm writing a report; don't want to either baffle with bullshit nor leave > >> >> out handy terms... > >> >> > >> >> -- > >> >> My liberal friends think I'm a conservative kook. > >> >> My conservative friends think I'm a liberal kook. > >> >> Why am I not happy that they have found common ground? > >> >> > >> >> Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com > >> > > >> >Nice thread, thanks Tim. > >> > > >> >I assume "Phaselock Techniques" by Flyod M. Gardener is the right > >> >book. (Making my Xmas wish list.) Any advantage of the third edition > >> >over the second? > >> > > >> >So in a type III system the error signal is integrated twice? > >> >Does anyone have an example where double integration is used? > >> >It doesn't have to be a PLL application any type of control loop would > >> >be fine. > >> > > >> >George H. > >> > >> I am a fan of the D-flop bang-bang phase detector. It has, in theory, > >> an infinite phase-error gain, which makes it interesting to analyze. > >> That's the way to go if you want to lock an oscillator to an external > >> input with picosecond long-term stability. > > > >The metastability problem is for real, though. Many moons ago (actually in the same DBS > >system I mentioned in the H parameters thread) I used a 75S74 as a frequency mixer in an > >offset loop to generate the pilot tones for the satellite uplink. Even with very clean > >input signals, when I looked at the d-flop output on a spectrum analyzer, the peak looked > >like one of those old-fashioned drinking fountains that ran all the time--it wobbled and > >bounced all over, especially at low modulation frequency. > > > >I'm really surprised that you can get good stability out of something that ugly. Or has the > >metastability issue somehow gone away since 1982? > > > >Cheers > > > >Phil Hobbs > > A D-flop, by itself, is only good with a VCO that's constrained to > less than 2:1 tuning range. Otherwise you can get harmonic locking... > not necessarily bad, I've used it to advantage... see my patents.My application was a pilot tone generator that needed to make 70 +- 10/11 MHz pilot tones. (Don't ask me why, that's what the system engineers came up with.) Instead of using two synthesizers, I made 70 MHz from the 10 MHz system clock, then used a 74LS92 plus a couple of gates (or some such thing) to divide the 10 MHz by 11, and then used the two halves of a 74S74 to generate the pilot tones. Because the mixing was so ugly, I wound up using a couple of crystal oscillators locked 1:1 to the d-flop outputs. It eventually worked fine, but the extreme ugliness of the output spectrum from those d-flops has stayed with me! Even if I'd used a nice diode-bridge mixer for the job, I'd probably still have needed the crystal oscillators, because the jitter spec was ridiculous. Cheers Phil Hobbs
Reply by ●October 13, 20122012-10-13
On Oct 12, 2:57�pm, Tim Wescott <t...@seemywebsite.com> wrote:> On Fri, 12 Oct 2012 09:29:55 -0700, George Herold wrote: > > On Oct 11, 4:36�pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> How commonly do you see PLL designs referred to as "type I", "type II", > >> "type III", etc.? �Do the terms make sense to you? > > >> I'm writing a report; don't want to either baffle with bullshit nor > >> leave out handy terms... > > >> -- > >> My liberal friends think I'm a conservative kook. My conservative > >> friends think I'm a liberal kook. Why am I not happy that they have > >> found common ground? > > >> Tim Wescott, Communications, Control, Circuits & > >> Softwarehttp://www.wescottdesign.com > > > Nice thread, thanks Tim. > > > I assume "Phaselock Techniques" by Flyod M. Gardener is the right book. > > (Making my Xmas wish list.) �Any advantage of the third edition over the > > second? > > > So in a type III system the error signal is integrated twice? Does > > anyone have an example where double integration is used? It doesn't have > > to be a PLL application any type of control loop would be fine. > > I've done it with gyroscopically stabilized platforms -- leave out the > second integrator and when you (or the world) pushes on it it moves over > and stays there until the push is gone. �Put the second integrator in and > it pushes back until it's in place. > > -- > My liberal friends think I'm a conservative kook. > My conservative friends think I'm a liberal kook. > Why am I not happy that they have found common ground? > > Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com- Hide quoted text - > > - Show quoted text -Interesting, what's the detector in a gyro? (I assume it was not an optical gyro.) George H.
Reply by ●October 13, 20122012-10-13
On Oct 13, 12:27�am, Tim Wescott <t...@seemywebsite.com> wrote:> On Sat, 13 Oct 2012 00:01:00 +0200, Jeroen wrote: > > On 2012-10-12 19:02, Tim Wescott wrote: > >> On Fri, 12 Oct 2012 12:08:46 +0200, Jeroen Belleman wrote: > > >>> On 2012-10-12 11:04, Robert Baer wrote: > >>>> Vladimir Vassilevsky wrote: > >>>>> "Tim Wescott"<t...@seemywebsite.com> wrote: > >>>>>> How commonly do you see PLL designs referred to as "type I", "type > >>>>>> II", "type III", etc.? Do the terms make sense to you? > > >>>>> IMO this terminology is used only in Gardner's book; there is no > >>>>> universal > >>>>> meaning. > >>>>> It is about P, PI, or PII control loop. Remnants of old times, when > >>>>> they used to mix the details of implementation with the type of the > >>>>> transfer function. > > >>>>>> I'm writing a report; don't want to either baffle with bullshit nor > >>>>>> leave > >>>>>> out handy terms... > > >>>>> Since nobody is going to read it anyway, why would that matter? > > >>>>> Vladimir Vassilevsky > >>>>> DSP and Mixed Signal Consultant > >>>>>www.abvolt.com > > >>>> Do not know but my wild uneducated guess is that "P" stands for > >>>> regular feedback as in a standard op-amp circuit, "PI" stands for > >>>> first derivative (eg: "P dot") and "PII" stands for second derivative > >>>> (eg: "P double dot"). > > >>> 'I' stands for an Integral term, not a derivative one. > > >>> I think that PLL designs should be classified by the number of > >>> significant poles and zeroes of their transfer functions. This 'type' > >>> business only introduces an extra layer of obscurity. > > >> Both the number of poles (order), and the number of nekkid integrators > >> (type) have relevance in telling you how the loop is going to behave. > > > Well yes, in essence that's what I said. We know what the poles and > > zeroes do. Introducing superfluous terminology like 'type' does not make > > it any clearer. I'd say: Drop the type. > > A type 0 loop can have a bazillion poles and still be type 0. > > A type 2 loop can have only two poles. > > Poles and type are _different_. > > -- > My liberal friends think I'm a conservative kook. > My conservative friends think I'm a liberal kook. > Why am I not happy that they have found common ground? > > Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com- Hide quoted text - > > - Show quoted text -OK Well I thought I was getting the type 'thing', but I'm confused again. First what's type zero? I was thinking about a (type I?) loop with just gain control that I've used to lock a diode laser to the side of an absorption line. You've got to put a (single pole) lowpass between the error signal and the gain, or it's pretty much an oscillator. George H.
Reply by ●October 13, 20122012-10-13
On Oct 13, 12:04�pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:> On Fri, 12 Oct 2012 09:29:55 -0700 (PDT), George Herold > > > > > > <gher...@teachspin.com> wrote: > >On Oct 11, 4:36 pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> How commonly do you see PLL designs referred to as "type I", "type II", > >> "type III", etc.? Do the terms make sense to you? > > >> I'm writing a report; don't want to either baffle with bullshit nor leave > >> out handy terms... > > >> -- > >> My liberal friends think I'm a conservative kook. > >> My conservative friends think I'm a liberal kook. > >> Why am I not happy that they have found common ground? > > >> Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com > > >Nice thread, thanks Tim. > > >I assume "Phaselock Techniques" by Flyod M. Gardener is the right > >book. �(Making my Xmas wish list.) �Any advantage of the third edition > >over the second? > > >So in a type III system the error signal is integrated twice? > >Does anyone have an example where double integration is used? > >It doesn't have to be a PLL application any type of control loop would > >be fine. > > >George H. > > I am a fan of the D-flop bang-bang phase detector. It has, in theory, > an infinite phase-error gain, which makes it interesting to analyze. > That's the way to go if you want to lock an oscillator to an external > input with picosecond long-term stability.Well no picoseconds, but I've used the switched gain AD630 for phase sensitive lockins George H.> > -- > > John Larkin � � � � � � � � �Highland Technology Incwww.highlandtechnology.com� jlarkin at highlandtechnology dot com > > Precision electronic instrumentation > Picosecond-resolution Digital Delay and Pulse generators > Custom timing and laser controllers > Photonics and fiberoptic TTL data links > VME �analog, thermocouple, LVDT, synchro, tachometer > Multichannel arbitrary waveform generators- Hide quoted text - > > - Show quoted text -
Reply by ●October 14, 20122012-10-14
On Sat, 13 Oct 2012 18:10:49 -0700, George Herold wrote:> On Oct 13, 12:27 am, Tim Wescott <t...@seemywebsite.com> wrote: >> On Sat, 13 Oct 2012 00:01:00 +0200, Jeroen wrote: >> > On 2012-10-12 19:02, Tim Wescott wrote: >> >> On Fri, 12 Oct 2012 12:08:46 +0200, Jeroen Belleman wrote: >> >> >>> On 2012-10-12 11:04, Robert Baer wrote: >> >>>> Vladimir Vassilevsky wrote: >> >>>>> "Tim Wescott"<t...@seemywebsite.com> wrote: >> >>>>>> How commonly do you see PLL designs referred to as "type I", >> >>>>>> "type II", "type III", etc.? Do the terms make sense to you? >> >> >>>>> IMO this terminology is used only in Gardner's book; there is no >> >>>>> universal >> >>>>> meaning. >> >>>>> It is about P, PI, or PII control loop. Remnants of old times, >> >>>>> when they used to mix the details of implementation with the type >> >>>>> of the transfer function. >> >> >>>>>> I'm writing a report; don't want to either baffle with bullshit >> >>>>>> nor leave >> >>>>>> out handy terms... >> >> >>>>> Since nobody is going to read it anyway, why would that matter? >> >> >>>>> Vladimir Vassilevsky >> >>>>> DSP and Mixed Signal Consultant >> >>>>>www.abvolt.com >> >> >>>> Do not know but my wild uneducated guess is that "P" stands for >> >>>> regular feedback as in a standard op-amp circuit, "PI" stands for >> >>>> first derivative (eg: "P dot") and "PII" stands for second >> >>>> derivative (eg: "P double dot"). >> >> >>> 'I' stands for an Integral term, not a derivative one. >> >> >>> I think that PLL designs should be classified by the number of >> >>> significant poles and zeroes of their transfer functions. This >> >>> 'type' business only introduces an extra layer of obscurity. >> >> >> Both the number of poles (order), and the number of nekkid >> >> integrators (type) have relevance in telling you how the loop is >> >> going to behave. >> >> > Well yes, in essence that's what I said. We know what the poles and >> > zeroes do. Introducing superfluous terminology like 'type' does not >> > make it any clearer. I'd say: Drop the type. >> >> A type 0 loop can have a bazillion poles and still be type 0. >> >> A type 2 loop can have only two poles. >> >> Poles and type are _different_. >> >> -- >> My liberal friends think I'm a conservative kook. My conservative >> friends think I'm a liberal kook. Why am I not happy that they have >> found common ground? >> >> Tim Wescott, Communications, Control, Circuits & >> Softwarehttp://www.wescottdesign.com- Hide quoted text - >> >> - Show quoted text - > > OK Well I thought I was getting the type 'thing', but I'm confused > again. > > First what's type zero? > I was thinking about a (type I?) loop with just gain control that I've > used to lock a diode laser to the side of an absorption line. You've > got to put a (single pole) lowpass between the error signal and the > gain, or it's pretty much an oscillator. > > George H.Type 0 is a loop that has no naked integrators (a low-pass isn't considered a naked integrator in this context, as it has finite DC gain). -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●October 14, 20122012-10-14
On Oct 14, 5:16�pm, Tim Wescott <t...@seemywebsite.com> wrote:> On Sat, 13 Oct 2012 18:10:49 -0700, George Herold wrote: > > On Oct 13, 12:27�am, Tim Wescott <t...@seemywebsite.com> wrote: > >> On Sat, 13 Oct 2012 00:01:00 +0200, Jeroen wrote: > >> > On 2012-10-12 19:02, Tim Wescott wrote: > >> >> On Fri, 12 Oct 2012 12:08:46 +0200, Jeroen Belleman wrote: > > >> >>> On 2012-10-12 11:04, Robert Baer wrote: > >> >>>> Vladimir Vassilevsky wrote: > >> >>>>> "Tim Wescott"<t...@seemywebsite.com> wrote: > >> >>>>>> How commonly do you see PLL designs referred to as "type I", > >> >>>>>> "type II", "type III", etc.? Do the terms make sense to you? > > >> >>>>> IMO this terminology is used only in Gardner's book; there is no > >> >>>>> universal > >> >>>>> meaning. > >> >>>>> It is about P, PI, or PII control loop. Remnants of old times, > >> >>>>> when they used to mix the details of implementation with the type > >> >>>>> of the transfer function. > > >> >>>>>> I'm writing a report; don't want to either baffle with bullshit > >> >>>>>> nor leave > >> >>>>>> out handy terms... > > >> >>>>> Since nobody is going to read it anyway, why would that matter? > > >> >>>>> Vladimir Vassilevsky > >> >>>>> DSP and Mixed Signal Consultant > >> >>>>>www.abvolt.com > > >> >>>> Do not know but my wild uneducated guess is that "P" stands for > >> >>>> regular feedback as in a standard op-amp circuit, "PI" stands for > >> >>>> first derivative (eg: "P dot") and "PII" stands for second > >> >>>> derivative (eg: "P double dot"). > > >> >>> 'I' stands for an Integral term, not a derivative one. > > >> >>> I think that PLL designs should be classified by the number of > >> >>> significant poles and zeroes of their transfer functions. This > >> >>> 'type' business only introduces an extra layer of obscurity. > > >> >> Both the number of poles (order), and the number of nekkid > >> >> integrators (type) have relevance in telling you how the loop is > >> >> going to behave. > > >> > Well yes, in essence that's what I said. We know what the poles and > >> > zeroes do. Introducing superfluous terminology like 'type' does not > >> > make it any clearer. I'd say: Drop the type. > > >> A type 0 loop can have a bazillion poles and still be type 0. > > >> A type 2 loop can have only two poles. > > >> Poles and type are _different_. > > >> -- > >> My liberal friends think I'm a conservative kook. My conservative > >> friends think I'm a liberal kook. Why am I not happy that they have > >> found common ground? > > >> Tim Wescott, Communications, Control, Circuits & > >> Softwarehttp://www.wescottdesign.com-Hide quoted text - > > >> - Show quoted text - > > > OK Well I thought I was getting the type 'thing', but I'm confused > > again. > > > First what's type zero? > > I was thinking about a (type I?) loop with just gain control that I've > > used to lock a diode laser to the side of an absorption line. �You've > > got to put a (single pole) lowpass between the error signal and the > > gain, or it's pretty much an oscillator. > > > George H. > > Type 0 is a loop that has no naked integrators (a low-pass isn't > considered a naked integrator in this context, as it has finite DC gain). > > -- > My liberal friends think I'm a conservative kook. > My conservative friends think I'm a liberal kook. > Why am I not happy that they have found common ground? > > Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com- Hide quoted text - > > - Show quoted text -Hmmm OK, For the diode laser locking thing, the piezo (plant) has a resonance a bit above 3kHz. Say I use a low pass filter with a 1 second time constant, and then crank up the gain til it's just below the oscillation point.... how 'naked' does the integrator need to be? (would 10 seconds and more gain count?) George H.
