On Wed, 31 Oct 2012 18:31:48 -0700 (PDT), dbd <dbd@ieee.org> wrote:>On Wednesday, October 31, 2012 10:56:26 AM UTC-7, SRB wrote: >> Hi SG >> ... >> It does surprise me that I'm not finding papers on this though... >> >> Thanks again, >> >> Sharon > >Have you tried Google? The words: > >multiple stage cic filter > >get such things as: > >http://www.indjst.org/archive/vol.4.issue.8/18-aug11anilsingh.pdf >Multistage implementation of multirate CIC filters >Anil Singh, Poonam Singhal and Rajeev Ratan >[Snipped by Lyons] Hi Dale, Those thieving bastards! They authors Singh, Singhal, and Ratan not only stole a figure directly from my March 2005 CIC article, "Understanding cascaded integrator-comb filters", http://www.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html they copied whole paragraphs, *WORD-FOR-WORD*, from my article. Not only are they plagiarists, they were too stupid to change my words to make their treachery less obvious. You cannot believe how much this kind of dishonesty ticks me off. Thanks for posting that URL Dale. [-Rick-]
Combining multiple CIC decimation filters in series
Started by ●October 31, 2012
Reply by ●November 1, 20122012-11-01
Reply by ●November 1, 20122012-11-01
On Thursday, November 1, 2012 12:07:21 PM UTC-7, Rick Lyons wrote: ...> Thanks for posting that URL Dale. > > [-Rick-]Rick I'm always happy to post references to your good stuff. Sometimes I just don't seem to know how happy I should be. Dale
Reply by ●November 2, 20122012-11-02
Hi Dale>A classic example of a design process aimed at achieving a filterspecific=>ation with resampling is the Goodman-Carey paper: >IEEE TRANSACTIONS ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL.ASSP-2S=>, NO.2, APRIL 1977 >Nine Digital Filters for Decimation and Interpolation >DAVID J. GOODMAN, MEMBER, IEEE, AND MICHAEL J. CAREYThank you very much for suggesting this paper - I'll take a look at it.>Whether the Goodman-Carey or any similar approach would be effective foryo=>ur application depends on your filter requirements and your implementation=>environment (which determines measures of resource cost: multiplies, adds,=>registers, logic blocks, etc.). Goodman-Carey combines CICs withadditional=> halfband filters. YMMV.Thanks, I'll bear that in mind. The DSP will be implemented on an fpga, probably using Xilinx ipcores (so I'm restricted to using the filters that Xilinx implement).>How did you pick multiple stages of CIC/resampler blocks?I'm still trying to work out the best way of doing this. So far I have just tested a few possible combinations. The example I gave in my original post was just based on trial-and-error / intuition which suggested that the order of the first CIC could be reduced with only a small loss of attenuation of aliased power. Sharon
Reply by ●November 2, 20122012-11-02
>Another alternative is to look at the Graychip documentation. The >Graychip is a configurable chip which consists of basebanding >capability followed by CIC and then followed by 2 FIR downsampling >filters (if memory serves correctly). In the documentation they give >several configurations which meet specific communication standards.Hi Dave Thanks for that suggestion. I'll take a look, Sharon
Reply by ●November 2, 20122012-11-02
>Hi Dale, > Those thieving bastards! They authors Singh, >Singhal, and Ratan not only stole a >figure directly from my March 2005 CIC article, >"Understanding cascaded integrator-comb filters", > >http://www.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html > >they copied whole paragraphs, *WORD-FOR-WORD*, from >my article. Not only are they plagiarists, they were >too stupid to change my words to make their treachery >less obvious.Hi Rick Yes I noticed the same thing, as I recognised the words from your book chapter on CICs. If you have any thoughts on the pros/cons of using more than one decimating CIC in series, I'd be grateful to hear them. Best wishes, Sharon
Reply by ●November 2, 20122012-11-02
On Friday, November 2, 2012 4:31:40 AM UTC-7, SRB wrote:> Thanks, I'll bear that in mind. The DSP will be implemented on an fpga, probably using Xilinx ipcores (so I'm restricted to using the filters that Xilinx implement).Certainly not restricted; FIR filters are easy to implement in HDL. The half band filters he mentioned are a class of linear phase FIR filters whose magnitude response is symmetric about fs/2. This has the attractive property of every other tap being zero, making them even easier to implement. If you implement this with an FIR ipcore, it may not be "smart" enough to not attempt a multiply by 0 every other tap.
Reply by ●November 2, 20122012-11-02
On Friday, November 2, 2012 7:06:15 AM UTC-7, Bryan wrote:> On Friday, November 2, 2012 4:31:40 AM UTC-7, SRB wrote: > Thanks, I'll bear that in mind. The DSP will be implemented on an fpga, probably using Xilinx ipcores (so I'm restricted to using the filters that Xilinx implement). Certainly not restricted; FIR filters are easy to implement in HDL. The half band filters he mentioned are a class of linear phase FIR filters whose magnitude response is symmetric about fs/2. This has the attractive property of every other tap being zero, making them even easier to implement. If you implement this with an FIR ipcore, it may not be "smart" enough to not attempt a multiply by 0 every other tap.Whoops: *fs/4
Reply by ●November 2, 20122012-11-02
>On Friday, November 2, 2012 7:06:15 AM UTC-7, Bryan wrote: >> On Friday, November 2, 2012 4:31:40 AM UTC-7, SRB wrote: > Thanks, I'llb=>ear that in mind. The DSP will be implemented on an fpga, probably usingXi=>linx ipcores (so I'm restricted to using the filters that Xilinximplement)=>. Certainly not restricted; FIR filters are easy to implement in HDL. Theh=>alf band filters he mentioned are a class of linear phase FIR filterswhose=> magnitude response is symmetric about fs/2. This has the attractiveproper=>ty of every other tap being zero, making them even easier to implement. If=>you implement this with an FIR ipcore, it may not be "smart" enough to not=>attempt a multiply by 0 every other tap. > >Whoops: *fs/4 >Hi Bryan The Xilinx docs for the FIR ipcore give a halfband decimation filter as one of the options, so it looks like it should be smart enough, as long as you tell it :-). Sharon
Reply by ●November 3, 20122012-11-03
On Fri, 02 Nov 2012 07:39:07 -0500, "SRB" <62352@dsprelated> wrote:> >>Hi Dale, >> Those thieving bastards! They authors Singh, >>Singhal, and Ratan not only stole a >>figure directly from my March 2005 CIC article, >>"Understanding cascaded integrator-comb filters", >> >>http://www.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html >> >>they copied whole paragraphs, *WORD-FOR-WORD*, from >>my article. Not only are they plagiarists, they were >>too stupid to change my words to make their treachery >>less obvious. > >Hi Rick > >Yes I noticed the same thing, as I recognised the words from your book >chapter on CICs. > >If you have any thoughts on the pros/cons of using more than one decimating >CIC in series, I'd be grateful to hear them. > >Best wishes, >SharonHello Sharon, Please excuse my cursing. (It always chaps my behind when I see someone take my work and present it as their own). You asked: "1) Do people typically combine multiple CIC filters in series in this way? and if not, why not?" The answer is yes. More than once I've seen papers showing lowpass decimation implementations where multiple cascaded CIC filters are used. That is where each CIC filter has its own decimation factor as you described. You also asked: "2) Are there any guidelines or rules of thumb as to how to select the number of filters to use and what decimation factor to use in each? (e.g. any publications similar to that of Crochiere and Rabiner 1975 for FIRs)" Oh shoot. I've never seen such an optimimization rule of thumb for cascaded CIC filters. I wonder if there isn't some way that you could use, or modify, Crochiere's and Rabiner's two-stage 'optimum decimation factors' equation so you could apply it to cascaded CIC filters. That would be a good homework problem. I wish I had time to think more about that. Sharon, if you're interested, send me a private E-mail and we'll arrange for me to send you the approriate errata for your copy of my DSP book. See Ya', [-Rick-]
Reply by ●November 3, 20122012-11-03
On 11/1/2012 3:07 PM, Rick Lyons wrote:> On Wed, 31 Oct 2012 18:31:48 -0700 (PDT), dbd<dbd@ieee.org> wrote: > >> On Wednesday, October 31, 2012 10:56:26 AM UTC-7, SRB wrote: >>> Hi SG >>> ... >>> It does surprise me that I'm not finding papers on this though... >>> >>> Thanks again, >>> >>> Sharon >> >> Have you tried Google? The words: >> >> multiple stage cic filter >> >> get such things as: >> >> http://www.indjst.org/archive/vol.4.issue.8/18-aug11anilsingh.pdf >> Multistage implementation of multirate CIC filters >> Anil Singh, Poonam Singhal and Rajeev Ratan >> > [Snipped by Lyons] > > Hi Dale, > Those thieving bastards! They authors Singh, > Singhal, and Ratan not only stole a > figure directly from my March 2005 CIC article, > "Understanding cascaded integrator-comb filters", > > http://www.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html > > they copied whole paragraphs, *WORD-FOR-WORD*, from > my article. Not only are they plagiarists, they were > too stupid to change my words to make their treachery > less obvious. > > You cannot believe how much this kind of dishonesty > ticks me off. > > Thanks for posting that URL Dale. > > [-Rick-]I can definitely understand your anger. It would tick me off too. I don't know if you did your own images for the article, but they look like someone put a lot of time into the project, both the content and the presentation. Do you plan to do anything? I would at least report this to the journal. I expect they would take this rather seriously. I know colleges check for this stuff in course papers. Rick
