Upsample, Downsample in the DSP audio Processing

>Tim Wescott  <tim@seemywebsite.com> wrote:
>
>>On Mon, 15 Jun 2015 15:54:46 -0500, Kathy_pdx wrote:
>
>>> It is an IIR filter. Since the EQ coefficients need be upsampled, the
>>> splines linear interpolation is not available since there is no end
>>> point.
>>> Due to the DSP processor constraints, the equalizer design has to be
>>> operated at 16 kHz/s.
>
>>Wait, wait.  In your original post you said that the ASIC was equipped
to 
>>do equalization, now you're saying that no, the equalization must happen

>>in the DSP.
>
>>What?
>
>I interpret this to mean that some black box being called "the DSP"
>is constrained to emit a set of filter coefficients computed for
>a filter running at 16 ks/sec, while some other box called "the ASIC"
>is being created to (presumably among other things) use them at 192
>ks/sec.
>
>Ideally the OP will clarify.
>
>Steve

Hi, Steve

 You are right. The EQ coefficients were calculated from 16 ks/s data by
DSP and the real EQ operation in 192 ks/s is done in the ASIC. The EQ
coefficients needs be up-sampled from 16 ks/s to 192 ks/s. It is a trade
off between the system complexity and cost in the overall system design. 

Thanks

Kathy

---------------------------------------
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On 15.06.15 22.54, Kathy_pdx wrote:
> It is an IIR filter. Since the EQ coefficients need be upsampled, the
> splines linear interpolation is not available since there is no end point.
> Due to the DSP processor constraints, the equalizer design has to be
> operated at 16 kHz/s.

You won't get too happy with this EQ, since it is bandwidth limited to 
about 7,5kHz. The IIR filter at 16 kHz can't process higher frequencies. 
So you do not have a adjusted response function for higher frequencies. 
I.e. phone quality.

However, you cannot simply upsample IIR coefficients. You need to keep 
the poles and zeros in place. This is normally a task for a Z 
transformation. But if your IIR is just a series of biquads (i.e. IIR 
filters of second order, not more) then it is quite easy. You can 
calculate the f0 and Q of each stage and calculate the new coefficients 
at the higher sampling rate from that.


Marcel

On 6/15/15 2:51 PM, Kathy_pdx wrote:
> The audio system sample rate is 192 kbits/s. The DSP audio processing
> involves the ASIC hardware and DSP processor. Due to the real-time
> constrains, the equalizer need be implemented at 16 kbits/s by a DSP
> processor. The routine way is to first down sample the audio signal to 16
> kbits/s, design an equalizer, then apply the equalizer to the audio signal
> at 16 kbits. Then the equalized audio signal is up sampled to 192 kbits/s.
> However, since our system has a ASIC hardware to support the equalizer
> operation at 192 kbits/s, it is more efficient to upsample the equalizer
> coefficients from 16 kbits/s to 192 kbits/s. Is there better way to
> upsample the equalizer coefficients from 16 kbits/s to 192 kbits/s except
> to repeat the equalizer coefficient 12 times?

it's hard for me to believe that the computational burden of 
downsampling, EQing at 16 kHz, and upsampling is less than just EQing at 
192 kHz.  how many bands or what order is your EQ?


-- 

r b-j                  rbj@audioimagination.com

"Imagination is more important than knowledge."

robert bristow-johnson  <rbj@audioimagination.com> wrote:

>On 6/15/15 2:51 PM, Kathy_pdx wrote:

>> The audio system sample rate is 192 kbits/s. The DSP audio processing
>> involves the ASIC hardware and DSP processor. Due to the real-time
>> constrains, the equalizer need be implemented at 16 kbits/s by a DSP
>> processor. The routine way is to first down sample the audio signal to 16
>> kbits/s, design an equalizer, then apply the equalizer to the audio signal
>> at 16 kbits. Then the equalized audio signal is up sampled to 192 kbits/s.
>> However, since our system has a ASIC hardware to support the equalizer
>> operation at 192 kbits/s, it is more efficient to upsample the equalizer
>> coefficients from 16 kbits/s to 192 kbits/s. Is there better way to
>> upsample the equalizer coefficients from 16 kbits/s to 192 kbits/s except
>> to repeat the equalizer coefficient 12 times?

>it's hard for me to believe that the computational burden of 
>downsampling, EQing at 16 kHz, and upsampling is less than just EQing at 
>192 kHz.  

I believe the two of your just said the exact same thing.


Steve

On Tue, 16 Jun 2015 00:19:55 -0500, Kathy_pdx wrote:

>>Tim Wescott  <tim@seemywebsite.com> wrote:
>>
>>>On Mon, 15 Jun 2015 15:54:46 -0500, Kathy_pdx wrote:
>>
>>>> It is an IIR filter. Since the EQ coefficients need be upsampled, the
>>>> splines linear interpolation is not available since there is no end
>>>> point.
>>>> Due to the DSP processor constraints, the equalizer design has to be
>>>> operated at 16 kHz/s.
>>
>>>Wait, wait.  In your original post you said that the ASIC was equipped
> to
>>>do equalization, now you're saying that no, the equalization must
>>>happen
> 
>>>in the DSP.
>>
>>>What?
>>
>>I interpret this to mean that some black box being called "the DSP" is
>>constrained to emit a set of filter coefficients computed for a filter
>>running at 16 ks/sec, while some other box called "the ASIC"
>>is being created to (presumably among other things) use them at 192
>>ks/sec.
>>
>>Ideally the OP will clarify.
>>
>>Steve
> 
> Hi, Steve
> 
>  You are right. The EQ coefficients were calculated from 16 ks/s data by
> DSP and the real EQ operation in 192 ks/s is done in the ASIC. The EQ
> coefficients needs be up-sampled from 16 ks/s to 192 ks/s. It is a trade
> off between the system complexity and cost in the overall system design.

Oooh, boy.  Now, where did I put my portrait of Diogenes of Sinope?  I 
need inspiration for this next bit.

If your boss is making you do this, expecting perfection, then brush up 
your resume.  If you're that boss and _your_ boss is competent, then 
brush up your resume.

In the mean time, I would take the equalizer coefficients, reverse-
engineer them into their continuous-time equivalents assuming something 
simple like a bilinear transformation with frequency warping, then 
forward-engineer them for a sampling rate of 192 ks/s.  If you're lucky 
there's an easy path to doing all of this in one step.

I would _not_ expect perfection, but if you're lucky it'll work at least 
as well as the old equalizer.

Ideally the coefficients that are available to you are already separated 
into 2nd-order transfer functions.

When you do all of this, you may wish to double-check that your ASIC has 
sufficiently wide data paths.  You're going up in sampling rate by a 
factor of 12.  If you are using 2nd order filters (you probably are, and 
they're probably biquads), then the minimum required width of your data 
paths and coefficient precisions has gone up by a little bit more than 7 
bits.  That's because the required width increase is roughly proportional 
to the square of the sampling rate increase, and 12^2 = 144 is closest to 
128 = 2^7.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com