Forums

BPSK one-bit

Started by Unknown July 24, 2015
Dear group,
I would like to implement a BPSK demodulator with one-bit signal processing.
I will use an Hard limiting IF and 1-bit A/D converter.
It is for coherent RADAR, so I have the clk.
I can sampling at maximum for time BW.

Any idea?

Thank you.
Best regards.

-- 
-- 


*Claudio Muzzini*Mob. +39 3484321716 

*Perfekt ist nicht genug.*
On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote:

> Dear group, > I would like to implement a BPSK demodulator with one-bit signal > processing. > I will use an Hard limiting IF and 1-bit A/D converter. > It is for coherent RADAR, so I have the clk. > I can sampling at maximum for time BW. > > Any idea? > > Thank you. > Best regards. > > --
What is your question? Do you have a specific issue you need help with, or do you want us to design your system for you? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha scritto:
> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: > > > Dear group, > > I would like to implement a BPSK demodulator with one-bit signal > > processing. > > I will use an Hard limiting IF and 1-bit A/D converter. > > It is for coherent RADAR, so I have the clk. > > I can sampling at maximum for time BW. > > > > Any idea? > > > > Thank you. > > Best regards. > > > > -- > > What is your question? Do you have a specific issue you need help with, > or do you want us to design your system for you? > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com
I need the idea how to implement, let me say - block diagram - principle schematic- -- -- *Claudio Muzzini*Mob. +39 3484321716 *Perfekt ist nicht genug.*
On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org
wrote:

>Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha scritto: >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >> >> > Dear group, >> > I would like to implement a BPSK demodulator with one-bit signal >> > processing. >> > I will use an Hard limiting IF and 1-bit A/D converter. >> > It is for coherent RADAR, so I have the clk. >> > I can sampling at maximum for time BW. >> > >> > Any idea? >> > >> > Thank you. >> > Best regards. >> > >> > -- >> >> What is your question? Do you have a specific issue you need help with, >> or do you want us to design your system for you? >> >> -- >> >> Tim Wescott >> Wescott Design Services >> http://www.wescottdesign.com > >I need the idea how to implement, let me say - block diagram - principle schematic-
The first block is the AFE, the Analog Front End, the next block is the ADC, the next block is the digital processing. Does that help? If not, you need to give more info.
>-- >-- > > >*Claudio Muzzini*Mob. +39 3484321716 > >*Perfekt ist nicht genug.*
Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha scritto:
> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org > wrote: > > >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha scritto: > >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: > >> > >> > Dear group, > >> > I would like to implement a BPSK demodulator with one-bit signal > >> > processing. > >> > I will use an Hard limiting IF and 1-bit A/D converter. > >> > It is for coherent RADAR, so I have the clk. > >> > I can sampling at maximum for time BW. > >> > > >> > Any idea? > >> > > >> > Thank you. > >> > Best regards. > >> > > >> > -- > >> > >> What is your question? Do you have a specific issue you need help with, > >> or do you want us to design your system for you? > >> > >> -- > >> > >> Tim Wescott > >> Wescott Design Services > >> http://www.wescottdesign.com > > > >I need the idea how to implement, let me say - block diagram - principle schematic- > > The first block is the AFE, the Analog Front End, the next block is > the ADC, the next block is the digital processing. > > Does that help? > > If not, you need to give more info. > > >-- > >-- > > > > > >*Claudio Muzzini*Mob. +39 3484321716 > > > >*Perfekt ist nicht genug.* > > Eric Jacobsen > Anchor Hill Communications > http://www.anchorhill.c
What about the Digital processing at "1-bit". If you know hot implement, please post the block diagram AND/OR the schematich. Best regards Claudio -- -- *Claudio Muzzini*Mob. +39 3484321716 *Perfekt ist nicht genug.*
On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote:

> Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha > scritto: >> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org >> wrote: >> >> >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha >> >scritto: >> >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >> >> >> >> > Dear group, >> >> > I would like to implement a BPSK demodulator with one-bit signal >> >> > processing. >> >> > I will use an Hard limiting IF and 1-bit A/D converter. >> >> > It is for coherent RADAR, so I have the clk. >> >> > I can sampling at maximum for time BW. >> >> > >> >> > Any idea? >> >> > >> >> > Thank you. >> >> > Best regards. >> >> > >> >> > -- >> >> >> >> What is your question? Do you have a specific issue you need help >> >> with, >> >> or do you want us to design your system for you? >> >> >> >> -- >> >> >> >> Tim Wescott Wescott Design Services http://www.wescottdesign.com >> > >> >I need the idea how to implement, let me say - block diagram - >> >principle schematic- >> >> The first block is the AFE, the Analog Front End, the next block is the >> ADC, the next block is the digital processing. >> >> Does that help? >> >> If not, you need to give more info. >> >> >-- >> >-- >> > >> > >> >*Claudio Muzzini*Mob. +39 3484321716 >> > >> >*Perfekt ist nicht genug.* >> >> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c > What about the Digital processing at "1-bit". > If you know hot implement, please post the block diagram AND/OR the > schematich.
This is sounding ever more like you want us to do your work for you. For the most part people on this group are willing to answer questions that take between on word and five paragraphs, and that don't require much effort beyond the writing to answer. So "is this block diagram sound" (with a link) is a good question, but "gimme a block diagram" is not, unless it's a block diagram for something bog-standard. This may sound harsh, but we're unpaid here. We are willing to help, if you can present us with suitable questions. Signal processing chains with "1-bit" ADCs look pretty much the same at the block diagram level as signal processing chains with wider ADCs (for that matter, it can look a lot like a signal processing chain with no ADC at all). The only real difference is that when you have a 1-bit ADC is that you need to (a) sample way fast, and (b) make sure that there's enough noise or other out-of-band signal. Basically, you need an ADC output that has enough signal buried in the noise so that when you average the snot out of it there's useful signal. I do not, personally, know of a good source for you. It sounds like you're doing something moderately unique -- I would suggest that you look for tutorials or white papers on other devices that use 1-bit ADCs (consumer-grade GPS receivers and possibly even cell phones that use spread spectrum would be good starting places), then see if you can't extrapolate from the 1-bit wisdom there to your problem. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
On Fri, 24 Jul 2015 14:20:11 -0700 (PDT), claudio.muzzini@muzzini.org
wrote:

>Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha scritto: >> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org >> wrote: >> >> >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha scritto: >> >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >> >> >> >> > Dear group, >> >> > I would like to implement a BPSK demodulator with one-bit signal >> >> > processing. >> >> > I will use an Hard limiting IF and 1-bit A/D converter. >> >> > It is for coherent RADAR, so I have the clk. >> >> > I can sampling at maximum for time BW. >> >> > >> >> > Any idea? >> >> > >> >> > Thank you. >> >> > Best regards. >> >> > >> >> > -- >> >> >> >> What is your question? Do you have a specific issue you need help with, >> >> or do you want us to design your system for you? >> >> >> >> -- >> >> >> >> Tim Wescott >> >> Wescott Design Services >> >> http://www.wescottdesign.com >> > >> >I need the idea how to implement, let me say - block diagram - principle schematic- >> >> The first block is the AFE, the Analog Front End, the next block is >> the ADC, the next block is the digital processing. >> >> Does that help? >> >> If not, you need to give more info. >> >> >-- >> >-- >> > >> > >> >*Claudio Muzzini*Mob. +39 3484321716 >> > >> >*Perfekt ist nicht genug.* >> >> Eric Jacobsen >> Anchor Hill Communications >> http://www.anchorhill.c >What about the Digital processing at "1-bit". >If you know hot implement, please post the block diagram AND/OR the schematich. >Best regards >Claudio
Nobody knows what you want until you ask an answerable question. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Il giorno sabato 25 luglio 2015 05:45:57 UTC+8, Tim Wescott ha scritto:
> On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote: > > > Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha > > scritto: > >> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org > >> wrote: > >> > >> >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha > >> >scritto: > >> >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: > >> >> > >> >> > Dear group, > >> >> > I would like to implement a BPSK demodulator with one-bit signal > >> >> > processing. > >> >> > I will use an Hard limiting IF and 1-bit A/D converter. > >> >> > It is for coherent RADAR, so I have the clk. > >> >> > I can sampling at maximum for time BW. > >> >> > > >> >> > Any idea? > >> >> > > >> >> > Thank you. > >> >> > Best regards. > >> >> > > >> >> > -- > >> >> > >> >> What is your question? Do you have a specific issue you need help > >> >> with, > >> >> or do you want us to design your system for you? > >> >> > >> >> -- > >> >> > >> >> Tim Wescott Wescott Design Services http://www.wescottdesign.com > >> > > >> >I need the idea how to implement, let me say - block diagram - > >> >principle schematic- > >> > >> The first block is the AFE, the Analog Front End, the next block is the > >> ADC, the next block is the digital processing. > >> > >> Does that help? > >> > >> If not, you need to give more info. > >> > >> >-- > >> >-- > >> > > >> > > >> >*Claudio Muzzini*Mob. +39 3484321716 > >> > > >> >*Perfekt ist nicht genug.* > >> > >> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c > > What about the Digital processing at "1-bit". > > If you know hot implement, please post the block diagram AND/OR the > > schematich. > > This is sounding ever more like you want us to do your work for you. For > the most part people on this group are willing to answer questions that > take between on word and five paragraphs, and that don't require much > effort beyond the writing to answer. So "is this block diagram > sound" (with a link) is a good question, but "gimme a block diagram" is > not, unless it's a block diagram for something bog-standard. > > This may sound harsh, but we're unpaid here. We are willing to help, if > you can present us with suitable questions. > > Signal processing chains with "1-bit" ADCs look pretty much the same at > the block diagram level as signal processing chains with wider ADCs (for > that matter, it can look a lot like a signal processing chain with no ADC > at all). > > The only real difference is that when you have a 1-bit ADC is that you > need to (a) sample way fast, and (b) make sure that there's enough noise > or other out-of-band signal. Basically, you need an ADC output that has > enough signal buried in the noise so that when you average the snot out > of it there's useful signal. > > I do not, personally, know of a good source for you. It sounds like > you're doing something moderately unique -- I would suggest that you look > for tutorials or white papers on other devices that use 1-bit ADCs > (consumer-grade GPS receivers and possibly even cell phones that use > spread spectrum would be good starting places), then see if you can't > extrapolate from the 1-bit wisdom there to your problem. > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com
Hello Tim, really thank you for your reply. If i need to design this demodulator with "standard" A/D for example 8bit, I do not have problem...I am a little bit confused about how to implement the filter after the multiplier(mixer) when I use only one bit. I do not want use FPGA but I would like to implement the demodulator with TTL logic Thank you -- -- *Claudio Muzzini*Mob. +39 3484321716 *Perfekt ist nicht genug.*
On Fri, 24 Jul 2015 23:16:11 -0700 (PDT), claudio.muzzini@muzzini.org
wrote:

>Il giorno sabato 25 luglio 2015 05:45:57 UTC+8, Tim Wescott ha scritto: >> On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote: >>=20 >> > Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha >> > scritto: >> >> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org >> >> wrote: >> >>=20 >> >> >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha >> >> >scritto: >> >> >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >> >> >>=20 >> >> >> > Dear group, >> >> >> > I would like to implement a BPSK demodulator with one-bit signal >> >> >> > processing. >> >> >> > I will use an Hard limiting IF and 1-bit A/D converter. >> >> >> > It is for coherent RADAR, so I have the clk. >> >> >> > I can sampling at maximum for time BW. >> >> >> >=20 >> >> >> > Any idea? >> >> >> >=20 >> >> >> > Thank you. >> >> >> > Best regards. >> >> >> >=20 >> >> >> > -- >> >> >>=20 >> >> >> What is your question? Do you have a specific issue you need help >> >> >> with, >> >> >> or do you want us to design your system for you? >> >> >>=20 >> >> >> -- >> >> >>=20 >> >> >> Tim Wescott Wescott Design Services http://www.wescottdesign.com >> >> > >> >> >I need the idea how to implement, let me say - block diagram - >> >> >principle schematic- >> >>=20 >> >> The first block is the AFE, the Analog Front End, the next block is th= >e >> >> ADC, the next block is the digital processing. >> >>=20 >> >> Does that help? >> >>=20 >> >> If not, you need to give more info. >> >>=20 >> >> >-- >> >> >-- >> >> > >> >> > >> >> >*Claudio Muzzini*Mob. +39 3484321716 >> >> > >> >> >*Perfekt ist nicht genug.* >> >>=20 >> >> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c >> > What about the Digital processing at "1-bit". >> > If you know hot implement, please post the block diagram AND/OR the >> > schematich. >>=20 >> This is sounding ever more like you want us to do your work for you. For= >=20 >> the most part people on this group are willing to answer questions that= >=20 >> take between on word and five paragraphs, and that don't require much=20 >> effort beyond the writing to answer. So "is this block diagram=20 >> sound" (with a link) is a good question, but "gimme a block diagram" is= >=20 >> not, unless it's a block diagram for something bog-standard. >>=20 >> This may sound harsh, but we're unpaid here. We are willing to help, if= >=20 >> you can present us with suitable questions. >>=20 >> Signal processing chains with "1-bit" ADCs look pretty much the same at= >=20 >> the block diagram level as signal processing chains with wider ADCs (for= >=20 >> that matter, it can look a lot like a signal processing chain with no ADC= >=20 >> at all). >>=20 >> The only real difference is that when you have a 1-bit ADC is that you=20 >> need to (a) sample way fast, and (b) make sure that there's enough noise= >=20 >> or other out-of-band signal. Basically, you need an ADC output that has= >=20 >> enough signal buried in the noise so that when you average the snot out= >=20 >> of it there's useful signal. >>=20 >> I do not, personally, know of a good source for you. It sounds like=20 >> you're doing something moderately unique -- I would suggest that you look= >=20 >> for tutorials or white papers on other devices that use 1-bit ADCs=20 >> (consumer-grade GPS receivers and possibly even cell phones that use=20 >> spread spectrum would be good starting places), then see if you can't=20 >> extrapolate from the 1-bit wisdom there to your problem. >>=20 >> --=20 >>=20 >> Tim Wescott >> Wescott Design Services >> http://www.wescottdesign.com > >Hello Tim, >really thank you for your reply. >If i need to design this demodulator with "standard" A/D for example 8bit, = >I do not have problem...I am a little bit confused about how to implement t= >he filter after the multiplier(mixer) when I use only one bit. I do not wan= >t use FPGA but I would like to implement the demodulator with TTL logic >Thank you
In general one can always trade sample rate for ADC precision, i.e., you can reduce the ADC precision by one bit if you increase the sample rate by a factor of four. So to reduce a eight-bit converter to one-bit, you need to increase the sample rate by a factor of 7x4 = 28. You can then get back to eight-bit precision by decimating the high-sample-rate down by the same factor of twenty-eight, and keeping eight of the bits gained in the accumulators in the decimating filter.
>*Perfekt ist nicht genug.*
Then you may never be happy. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
On 25.07.2015 9:16, claudio.muzzini@muzzini.org wrote:
> Il giorno sabato 25 luglio 2015 05:45:57 UTC+8, Tim Wescott ha scritto: >> On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote: >> >>> Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha >>> scritto: >>>> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org >>>> wrote: >>>> >>>>> Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha >>>>> scritto: >>>>>> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >>>>>> >>>>>>> Dear group, >>>>>>> I would like to implement a BPSK demodulator with one-bit signal >>>>>>> processing. >>>>>>> I will use an Hard limiting IF and 1-bit A/D converter. >>>>>>> It is for coherent RADAR, so I have the clk. >>>>>>> I can sampling at maximum for time BW. >>>>>>> >>>>>>> Any idea? >>>>>>> >>>>>>> Thank you. >>>>>>> Best regards. >>>>>>> >>>>>>> -- >>>>>> >>>>>> What is your question? Do you have a specific issue you need help >>>>>> with, >>>>>> or do you want us to design your system for you? >>>>>> >>>>>> -- >>>>>> >>>>>> Tim Wescott Wescott Design Services http://www.wescottdesign.com >>>>> >>>>> I need the idea how to implement, let me say - block diagram - >>>>> principle schematic- >>>> >>>> The first block is the AFE, the Analog Front End, the next block is the >>>> ADC, the next block is the digital processing. >>>> >>>> Does that help? >>>> >>>> If not, you need to give more info. >>>> >>>>> -- >>>>> -- >>>>> >>>>> >>>>> *Claudio Muzzini*Mob. +39 3484321716 >>>>> >>>>> *Perfekt ist nicht genug.* >>>> >>>> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c >>> What about the Digital processing at "1-bit". >>> If you know hot implement, please post the block diagram AND/OR the >>> schematich. >> >> This is sounding ever more like you want us to do your work for you. For >> the most part people on this group are willing to answer questions that >> take between on word and five paragraphs, and that don't require much >> effort beyond the writing to answer. So "is this block diagram >> sound" (with a link) is a good question, but "gimme a block diagram" is >> not, unless it's a block diagram for something bog-standard. >> >> This may sound harsh, but we're unpaid here. We are willing to help, if >> you can present us with suitable questions. >> >> Signal processing chains with "1-bit" ADCs look pretty much the same at >> the block diagram level as signal processing chains with wider ADCs (for >> that matter, it can look a lot like a signal processing chain with no ADC >> at all). >> >> The only real difference is that when you have a 1-bit ADC is that you >> need to (a) sample way fast, and (b) make sure that there's enough noise >> or other out-of-band signal. Basically, you need an ADC output that has >> enough signal buried in the noise so that when you average the snot out >> of it there's useful signal. >> >> I do not, personally, know of a good source for you. It sounds like >> you're doing something moderately unique -- I would suggest that you look >> for tutorials or white papers on other devices that use 1-bit ADCs >> (consumer-grade GPS receivers and possibly even cell phones that use >> spread spectrum would be good starting places), then see if you can't >> extrapolate from the 1-bit wisdom there to your problem. >> >> -- >> >> Tim Wescott >> Wescott Design Services >> http://www.wescottdesign.com > > Hello Tim, > really thank you for your reply. > If i need to design this demodulator with "standard" A/D for example 8bit, I do not have problem...I am a little bit confused about how to implement the filter after the multiplier(mixer) when I use only one bit. I do not want use FPGA but I would like to implement the demodulator with TTL logic > Thank you >
I thought the entire point of FPGAs was to simplify digital design. But if you are planning to use discreet components anyway, what is the reason to make it digital? There are a lot of schematics for analog demodulators. You can look up any older book, e.g. 1973 "Telecommunication Systems Engineering" by Lindsey and Simon, which can be used to build an analog BPSK demodulator. Regards, Evgeny.