Impact of complex limiter on BPSK BER

Vladimir Vassilevsky wrote:

> The limiter will definitely impact your AWGN BER. The loss is as high as 
> about 1dB at the reasonable BERs of 0.01...0.001. It is going to be much 
> worse with CW interference.
> 
> Vladimir Vassilevsky
> 
> DSP and Mixed Signal Design Consultant
> 
> http://www.abvolt.com
-snip-

I think (I hope!) that he's only using the limiting in the clock 
recovery leg of his algorithm.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Vladimir Vassilevsky wrote:

> The limiter will definitely impact your AWGN BER. The loss is as high as 
> about 1dB at the reasonable BERs of 0.01...0.001. It is going to be much 
> worse with CW interference.
> 
> Vladimir Vassilevsky
> 
> DSP and Mixed Signal Design Consultant
> 
> http://www.abvolt.com
> 
> 
-snip-

I think (I hope!) that he's only using the limiting in the clock 
recovery leg of his algorithm.  If so, then various interference will 
impact his clock recovery, but until the PLL was affected it wouldn't 
touch the AWGN BER -- CW interference would still make things go to 
hell, of course.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

On 31 Oct 2004 02:55:37 -0800, johns@xetron.com (John Sampson) wrote:

>eric.jacobsen@ieee.org (Eric Jacobsen) wrote in message news:<418402ce.49473765@news.west.cox.net>...

>> How are you implementing the complex limiter?   It needs to be in
>> polar form so that the magnitude of the vector is limited and the
>> phase unaffected.   I _think_ this is what you mean by a complex
>> limiter, so I hope that's already what you're doing.   If you just
>> limit I and Q independently you will add phase distortion which will
>> do nasty things to the carrier recovery loop.  The difference is
>> whether you're limiting magnitude within a circle or a square.  Circle
>> good; square bad.
>
>Circle. I divide each complex sample by its magnitude.
>
>> 
>> Depending on the phase detector you're using for your symbol recovery
>> loop, it may not like limiting at all.   Make sure the symbol recovery
>> phase detector is appropriate for use in a system with hard limiting.
>
>The complex limited, match filtered data is passed through a nonlinearity
>(half-bit delay-conjugate-multiply, keep real part) and a 2nd order IIR
>BPF. Then a 2nd order PLL is locked to that. The phase detector is simple,
>just sample the NCO on rising edges of the BPF. 

Hmm.  I know people have implemented loops that way, but I don't have
any experience with that particular method for symbol clock recovery.
My suspicion was always that there may be some loss associated with
doing things that way, but I don't know for certain.

>> It sounds like you're using an integrate and dump filter if you're
>> trying to match to rectangular pulses.   This is fine if it fits your
>> application, and there is a ton of literature on how to build loops
>> around these.   Do you limit before or after the integrate and dump?
>
>The integrate and dump is a sliding one bit boxcar, before the complex
>limiter and before symbol timing and carrier recovery. I have interchanged
>the complex liminter and matched filter, not much difference noticed.
>
>> 
>> BTW, your goal is attainable.  I've seen modems with 70MHz IF come off
>> production lines with end-to-end implementation loss of 0.3dB.  That's
>> the edge of the distribution, and typical was 0.4-0.5dB.  Getting
>> 0.2-0.3dB at the baseband is definitely attainable.
>> Digital-to-digital you can get it close enough that it's hard to
>> measure.
>
>Out of curiosity, down to what BER did that performance hold? I probably
>have one of your old modems at work somewhere.

That was when I worked at EFData, so if you have any EFData satellite
modems laying around, you may have an example of what I was noting.

>I am getting results distributed from 0.1-0.7 dB, digital to digital. The demod
>has 8 different data rates, and the IL varies by data rate. It also varies
>depending on how many ppm bit timing error I introduce. I am using a 
>fractional decimator based on a cubic polynomial to get to integer samples/bit,
>and the IL seems to worsen as the decimation ratio goes down. Decimating by 
>a number close to 1 seems to work best.

You lost me.  What's IL?

Eric Jacobsen
Minister of Algorithms, Intel Corp.
My opinions may not be Intel's opinions.
http://www.ericjacobsen.org

"Eric Jacobsen" <eric.jacobsen@ieee.org> wrote in message
news:41869b50.219587921@news.west.cox.net...
> On 31 Oct 2004 02:55:37 -0800, johns@xetron.com (John Sampson) wrote:
>
> >eric.jacobsen@ieee.org (Eric Jacobsen) wrote in message
news:<418402ce.49473765@news.west.cox.net>...
>
> >> How are you implementing the complex limiter?   It needs to be in
> >> polar form so that the magnitude of the vector is limited and the
> >> phase unaffected.   I _think_ this is what you mean by a complex
> >> limiter, so I hope that's already what you're doing.   If you just
> >> limit I and Q independently you will add phase distortion which will
> >> do nasty things to the carrier recovery loop.  The difference is
> >> whether you're limiting magnitude within a circle or a square.  Circle
> >> good; square bad.
> >
> >Circle. I divide each complex sample by its magnitude.
> >
> >>
> >> Depending on the phase detector you're using for your symbol recovery
> >> loop, it may not like limiting at all.   Make sure the symbol recovery
> >> phase detector is appropriate for use in a system with hard limiting.
> >
> >The complex limited, match filtered data is passed through a nonlinearity
> >(half-bit delay-conjugate-multiply, keep real part) and a 2nd order IIR
> >BPF. Then a 2nd order PLL is locked to that. The phase detector is
simple,
> >just sample the NCO on rising edges of the BPF.
>
> Hmm.  I know people have implemented loops that way, but I don't have
> any experience with that particular method for symbol clock recovery.
> My suspicion was always that there may be some loss associated with
> doing things that way, but I don't know for certain.
>
> >> It sounds like you're using an integrate and dump filter if you're
> >> trying to match to rectangular pulses.   This is fine if it fits your
> >> application, and there is a ton of literature on how to build loops
> >> around these.   Do you limit before or after the integrate and dump?
> >
> >The integrate and dump is a sliding one bit boxcar, before the complex
> >limiter and before symbol timing and carrier recovery. I have
interchanged
> >the complex liminter and matched filter, not much difference noticed.
> >
> >>
> >> BTW, your goal is attainable.  I've seen modems with 70MHz IF come off
> >> production lines with end-to-end implementation loss of 0.3dB.  That's
> >> the edge of the distribution, and typical was 0.4-0.5dB.  Getting
> >> 0.2-0.3dB at the baseband is definitely attainable.
> >> Digital-to-digital you can get it close enough that it's hard to
> >> measure.
> >
> >Out of curiosity, down to what BER did that performance hold? I probably
> >have one of your old modems at work somewhere.
>
> That was when I worked at EFData, so if you have any EFData satellite
> modems laying around, you may have an example of what I was noting.
>
> >I am getting results distributed from 0.1-0.7 dB, digital to digital. The
demod
> >has 8 different data rates, and the IL varies by data rate. It also
varies
> >depending on how many ppm bit timing error I introduce. I am using a
> >fractional decimator based on a cubic polynomial to get to integer
samples/bit,
> >and the IL seems to worsen as the decimation ratio goes down. Decimating
by
> >a number close to 1 seems to work best.
>
> You lost me.  What's IL?
>
> Eric Jacobsen
> Minister of Algorithms, Intel Corp.
> My opinions may not be Intel's opinions.
> http://www.ericjacobsen.org
Suspect John may be using IL as acronym for implementation loss.

eric.jacobsen@ieee.org (Eric Jacobsen) wrote in message news:<41869b50.219587921@news.west.cox.net>...
> On 31 Oct 2004 02:55:37 -0800, johns@xetron.com (John Sampson) wrote:
> 
> >eric.jacobsen@ieee.org (Eric Jacobsen) wrote in message news:<418402ce.49473765@news.west.cox.net>...
>  
> >> How are you implementing the complex limiter?   It needs to be in
> >> polar form so that the magnitude of the vector is limited and the
> >> phase unaffected.   I _think_ this is what you mean by a complex
> >> limiter, so I hope that's already what you're doing.   If you just
> >> limit I and Q independently you will add phase distortion which will
> >> do nasty things to the carrier recovery loop.  The difference is
> >> whether you're limiting magnitude within a circle or a square.  Circle
> >> good; square bad.
> >
> >Circle. I divide each complex sample by its magnitude.
> >
> >> 
> >> Depending on the phase detector you're using for your symbol recovery
> >> loop, it may not like limiting at all.   Make sure the symbol recovery
> >> phase detector is appropriate for use in a system with hard limiting.
> >
> >The complex limited, match filtered data is passed through a nonlinearity
> >(half-bit delay-conjugate-multiply, keep real part) and a 2nd order IIR
> >BPF. Then a 2nd order PLL is locked to that. The phase detector is simple,
> >just sample the NCO on rising edges of the BPF. 
> 
> Hmm.  I know people have implemented loops that way, but I don't have
> any experience with that particular method for symbol clock recovery.
> My suspicion was always that there may be some loss associated with
> doing things that way, but I don't know for certain.
> 
> >> It sounds like you're using an integrate and dump filter if you're
> >> trying to match to rectangular pulses.   This is fine if it fits your
> >> application, and there is a ton of literature on how to build loops
> >> around these.   Do you limit before or after the integrate and dump?
> >
> >The integrate and dump is a sliding one bit boxcar, before the complex
> >limiter and before symbol timing and carrier recovery. I have interchanged
> >the complex liminter and matched filter, not much difference noticed.
> >
> >> 
> >> BTW, your goal is attainable.  I've seen modems with 70MHz IF come off
> >> production lines with end-to-end implementation loss of 0.3dB.  That's
> >> the edge of the distribution, and typical was 0.4-0.5dB.  Getting
> >> 0.2-0.3dB at the baseband is definitely attainable.
> >> Digital-to-digital you can get it close enough that it's hard to
> >> measure.
> >
> >Out of curiosity, down to what BER did that performance hold? I probably
> >have one of your old modems at work somewhere.
> 
> That was when I worked at EFData, so if you have any EFData satellite
> modems laying around, you may have an example of what I was noting.

Yep.

> 
> >I am getting results distributed from 0.1-0.7 dB, digital to digital. The demod
> >has 8 different data rates, and the IL varies by data rate. It also varies
> >depending on how many ppm bit timing error I introduce. I am using a 
> >fractional decimator based on a cubic polynomial to get to integer samples/bit,
> >and the IL seems to worsen as the decimation ratio goes down. Decimating by 
> >a number close to 1 seems to work best.
> 
> You lost me.  What's IL?

IL = implementation loss.

Tim Wescott <tim@wescottnospamdesign.com> wrote in message news:<10ocp2tkdnu3a3d@corp.supernews.com>...
> Vladimir Vassilevsky wrote:
> 
> > The limiter will definitely impact your AWGN BER. The loss is as high as 
> > about 1dB at the reasonable BERs of 0.01...0.001. It is going to be much 
> > worse with CW interference.
> > 
> > Vladimir Vassilevsky
> > 
> > DSP and Mixed Signal Design Consultant
> > 
> > http://www.abvolt.com
> > 
> > 
> -snip-
> 
> I think (I hope!) that he's only using the limiting in the clock 
> recovery leg of his algorithm.  If so, then various interference will 
> impact his clock recovery, but until the PLL was affected it wouldn't 
> touch the AWGN BER -- CW interference would still make things go to 
> hell, of course.

The limiter is placed in the main signal path before clock recovery,
carrier tracking, and bit detection. It is not clear to me how the
limiter degrades BER more in the presence of CW interference than
would be the case without it. It does not change the phase of the
signal -- can you explain?

Thanks,

John

John Sampson wrote:

> 
> The limiter is placed in the main signal path before clock recovery,
> carrier tracking, and bit detection. It is not clear to me how the
> limiter degrades BER more in the presence of CW interference than
> would be the case without it. It does not change the phase of the
> signal -- can you explain?
> 

Limiting is lossy operation. If the error is bigger then the signal then 
the limiter will produce the maximum wrong output no matter how much the 
  error is bigger then the signal. The impact of error depends on its 
pdf. CW interference is much worse in this case then the AWGN.
My best advice will be take the mathlab, model it and see everything 
yourself.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

johns@xetron.com (John Sampson) wrote in message news:<ae739955.0410290528.11350306@posting.google.com>...
> I am working on a fixed-point DSP-based coherent BPSK modem. In order
> to improve the computational dynamic range of the clock recovery and
> carrier tracking algorithms, I put a complex limiter on the complex
> baseband. It comes after the signal has been filtered with a
> rectangular pulse with length equal to one bit time. What it does is
> compute phi=atan2(y/x) and then looks up sin(phi) and cos(phi) in a
> table.
> 
> The goal here is to have an implementation loss of a few tenths of a
> dB in AWGN at 10% BER and above. In tracking down tenths of dB's, I
> have wondered if the complex limiter might actually reduce sensitivity
> by folding some noise in band. So far, taking it out has screwed up
> the clock and carrier recovery so I can't make an assessment.
> 
> Any comments?
> 
> Thanks,
> 
> John

Hi Guys
This is a great thread.  Can anyone recommend any books that discuss
the pros and cons of different approaches to software modems (much
like this thread is doing).  I find that my digital communications
books tend to simply present the maths and conclude "This is how it is
done" rather than putting forward different techniques and how they
affect the modem.  I am guessing that discussions like this are
generally found on the user net and technical papers rather than
commercial text books.

Any recommendations? :-)
Cheers
Tim

tim_ward_123@hotmail.com (Tim) wrote in message news:<44e5a88d.0411040050.e1b7e87@posting.google.com>...
> johns@xetron.com (John Sampson) wrote in message news:<ae739955.0410290528.11350306@posting.google.com>...
> > I am working on a fixed-point DSP-based coherent BPSK modem. In order
> > to improve the computational dynamic range of the clock recovery and
> > carrier tracking algorithms, I put a complex limiter on the complex
> > baseband. It comes after the signal has been filtered with a
> > rectangular pulse with length equal to one bit time. What it does is
> > compute phi=atan2(y/x) and then looks up sin(phi) and cos(phi) in a
> > table.
> > 
> > The goal here is to have an implementation loss of a few tenths of a
> > dB in AWGN at 10% BER and above. In tracking down tenths of dB's, I
> > have wondered if the complex limiter might actually reduce sensitivity
> > by folding some noise in band. So far, taking it out has screwed up
> > the clock and carrier recovery so I can't make an assessment.
> > 
> > Any comments?
> > 
> > Thanks,
> > 
> > John
> 
> Hi Guys
> This is a great thread.  Can anyone recommend any books that discuss
> the pros and cons of different approaches to software modems (much
> like this thread is doing).  I find that my digital communications
> books tend to simply present the maths and conclude "This is how it is
> done" rather than putting forward different techniques and how they
> affect the modem.  I am guessing that discussions like this are
> generally found on the user net and technical papers rather than
> commercial text books.
> 
> Any recommendations? :-)
> Cheers
> Tim

Here are some from my bookshelf. Probably no surprises on this list,
but some of these have lots of comparisons.

DIGITAL COMMUNICATION RECEIVERS, Meyr & Moeneclaey & Fechtel - Wiley
SYNCHRONIZATION IN DIGITAL COMMUNICATIONS, Meyr & Ascheid - Wiley
SYNCHRONIZATION TECHNIQUES FOR DIGITAL RECEIVERS, Mengali & D'Andrea - KA/PP
TELECOMMUNICATIONS SYSTEMS ENGINEERING, Lindsey & Simon - Dover
THEORY AND PRACTICE OF MODEM DESIGN, Bingham - Wiley
DIGITAL COMMUNICATION TECHNIQUES - Simon & Hinedi & Lindsey - Prentice Hall
WIRELESS DIGITAL COMMUNICATIONS: DESIGN & THEORY - McDermott - TAPR

John