Hello, I'm going to implement a decimating CIC filter (inside an FPGA chip), but there are three unclear details. Could you please explain me them? 1. How should I connect integrators (and combs)? The number of accumulator bits (let's call it N) can be easily computed, but how wide should be the buses interconnecting CIC stages? Should I pass all N bits between every n-th and (n+1)-th stage or perhaps a smaller fraction of it? 2. The value of N is quite big (45--50 bits), so it would be nice to decrease it considerably. I know that it is possible to reduce this value for a given set of parameters (input and output widths) by discarding M least significant bits, but I have no papers about it, just an example of a reduced filter. So, how can I calculate the new width (N-M) of accumulators or -- if it's not so simple -- how wide should an accumulator be for 18-bit input and 24-bit output? 3. May I move a CIC filter in a chain of several CIC filters? For example, I have a 2-nd order and 5-th order decimating CIC. Is it possible to use "input => 5-th order CIC => 2-th order CIC => output" instead of more classic form "input => 2-th order CIC => 5-th order CIC => output"? Theoretically there's no problem, but are there any practical obstacles? Best regards Piotr Wyderski

# CIC filters

Started by ●April 4, 2005

Posted by ●April 4, 2005

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message news:d2rdfn$2h0$1@news.dialog.net.pl...> Hello, > > I'm going to implement a decimating CIC filter (inside an FPGA chip), > but there are three unclear details. Could you please explain me them? > > 1. How should I connect integrators (and combs)? The number of > accumulator bits (let's call it N) can be easily computed, but how > wide should be the buses interconnecting CIC stages? Should > I pass all N bits between every n-th and (n+1)-th stage or perhaps > a smaller fraction of it? > > 2. The value of N is quite big (45--50 bits), so it would be nice > to decrease it considerably. I know that it is possible to reduce > this value for a given set of parameters (input and output widths) > by discarding M least significant bits, but I have no papers about > it, just an example of a reduced filter. So, how can I calculate the > new width (N-M) of accumulators or -- if it's not so simple -- how > wide should an accumulator be for 18-bit input and 24-bit output? > > 3. May I move a CIC filter in a chain of several CIC filters? > For example, I have a 2-nd order and 5-th order decimating > CIC. Is it possible to use "input => 5-th order CIC => 2-th order CIC > => output" instead of more classic form "input => 2-th order CIC > => 5-th order CIC => output"? Theoretically there's no problem, but > are there any practical obstacles? > > Best regards > Piotr Wyderski >Have you seen this http://www.xilinx.com/ipcenter/catalog/logicore/docs/C_CIC_V1_0.pdf ? and this http://users.snip.net/~donadio/cic.pdf ? 1) Don't cascade CICs, mess around with the size and characteristics of one big one. 2) The bit growth is determined by the CIC parameters. For a 24 bit output, just use the top 24 bits, although I'm not sure that makes much sense if your input is only 18 bits. I suppose you have some noise shaping going on so this is a good idea? 3) See answer 1) Cheers, Syms.

Posted by ●April 5, 2005

Symon wrote:> Have you seen this > http://www.xilinx.com/ipcenter/catalog/logicore/docs/C_CIC_V1_0.pdf ?No, thanks!> and this http://users.snip.net/~donadio/cic.pdf ?Yes, I have seen this one.> 1) Don't cascade CICs, mess around with the size and characteristics ofone> big one.Is it a good idea to have a single CIC with decimation rate of 4096 or more?> 2) The bit growth is determined by the CIC parameters. For a 24 bitoutput,> just use the top 24 bits, although I'm not sure that makes much sense if > your input is only 18 bits. I suppose you have some noise shaping going on > so this is a good idea?What noise shaping? The input stream will be taken directly from a quadrature mixer, similarly as in AD6624. Best regards Piotr Wyderski