James Cotton <peabody124@gmail.com> wrote in news:pan.2005.04.15.01.25.34.239178@gmail.com:> I probably could start w/ an eval board, but this is being designed > for an EEG system so needs to be isolated well. If I were to use an > eval board I would have either have to build a board w/ a bunch of > isolation amplifier (expensive part count) or an isolated ADC which > would probably be fairly easy. However, half the fun is the design > and layout and eventually I'll want to make my own version anyway, so > I figured I might as well start that way - esp. w/ the low signal > count. It will probably be working at fairly high frequencies to > preprocess as much as possible b4 sending it to the computer. If I > got enough caps underneath the thing would my chances be decent or am > I more likely to get dodgy than not? > > Also, w/ regards to decoupling, I notice most of the schematics online > for the eval boards show many caps of a handful of values - I know > this is to get best filtering at various frequencies, but what is the > optimal placement plan. One cap per pin, regardless of value, and try > and space them out? One of each value at a couple of local star > supplies? Even distributed between a power ring and large ground pour > w/ the pins making connections to the power ring wherever convenient? > > Thanks, > James > > On Wed, 13 Apr 2005 12:31:43 -0700, Clay wrote: > >> >> James Cotton wrote: >>> I am designing a board with a TMS320F2811 chip, and have the >> schematic >>> done. I was about to start the layout but I wanted to ask if it can >> work >>> to make a double layered board (i saw a similar thread a while back, >> but >>> it didn't seem to answer this directly). I am only going to be >>> using >> the >>> SCI pins and the analog inputs, so routing should be feasible. I >>> was thinking about laying a ground plane under the chip and then a >>> core >> supply >>> ring around that and a IO supply around that (C shapes, not complete >>> circle) on the bottom layer, then decoupling capacitors on the >>> bottom >> too >>> right below their respective pins. Is this feasible (college >> student, >>> just trying to save a buck on PCB manufacturing). >>> >>> Thank you, >>> James >> >> Hello James, >> This is a question with a not so simple answer. Certianly you have >> the number of signals quite low, so routing them is not a real issue. >> But you have started thinking about the real problem. Namely can you >> get the power into the chip quietly. Most modern cpus have multiple >> power pins where each pin powers a different portion of the chip. So >> sometimes when you have improper decoupling, some functions in the >> chip work while others act "dodgy." >> >> You "c" rings just may work - just pour as much copper as you can and >> provide multiple decoupling caps. However any high speed design I >> would do would have at least 4 layers. >> >> Do you really need a custom board, or can you get an eval board and >> add on your stuff - either in a breadboard region or as a daughter >> board? >> >> IHTH, >> Clay >James, I think you are going to get into trouble with a two layer pcb. You should use 4 layers. I would use 1 layer for ground and 1 for power. If there is a core voltage lower than 3.3V, I would pour that layer under the part. Often this can be the same layer as the I/O supply (3.3V). If your part uses an internal PLL for clock multiplication, you must have a very good layout. Two layers will be probably be a disaster. I use 10nF caps for most of my decoupling (0805 or 0603 SMT). Do not use leaded parts for this. I try to layout the caps around the IC so that the positive connection is close to the power pins. Make sure the ground returns go directly tho the ground plane. I also usually use a few .1uF caps for each supply. The thing to remember is there is no such thing as a capacitor. There are only devices that approximate capacitors. This is why we use different values for decoupling. Our boards separate the DSP engine from the I/O functions (two boards). You might take a look at our special promo package. This is a system based on an Analog Devices SHARC and an Altera FPGA for only $200. It comes with a built in debugger and is supported by Visual DSP. The boards work like an EZ-Kit with more flexibility. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
double layered bords
Started by ●April 13, 2005
Reply by ●April 22, 20052005-04-22
Reply by ●April 22, 20052005-04-22
James Cotton <peabody124@gmail.com> wrote in news:pan.2005.04.15.01.25.34.239178@gmail.com:> I probably could start w/ an eval board, but this is being designed > for an EEG system so needs to be isolated well. If I were to use an > eval board I would have either have to build a board w/ a bunch of > isolation amplifier (expensive part count) or an isolated ADC which > would probably be fairly easy. However, half the fun is the design > and layout and eventually I'll want to make my own version anyway, so > I figured I might as well start that way - esp. w/ the low signal > count. It will probably be working at fairly high frequencies to > preprocess as much as possible b4 sending it to the computer. If I > got enough caps underneath the thing would my chances be decent or am > I more likely to get dodgy than not? > > Also, w/ regards to decoupling, I notice most of the schematics online > for the eval boards show many caps of a handful of values - I know > this is to get best filtering at various frequencies, but what is the > optimal placement plan. One cap per pin, regardless of value, and try > and space them out? One of each value at a couple of local star > supplies? Even distributed between a power ring and large ground pour > w/ the pins making connections to the power ring wherever convenient? > > Thanks, > James > > On Wed, 13 Apr 2005 12:31:43 -0700, Clay wrote: > >> >> James Cotton wrote: >>> I am designing a board with a TMS320F2811 chip, and have the >> schematic >>> done. I was about to start the layout but I wanted to ask if it can >> work >>> to make a double layered board (i saw a similar thread a while back, >> but >>> it didn't seem to answer this directly). I am only going to be >>> using >> the >>> SCI pins and the analog inputs, so routing should be feasible. I >>> was thinking about laying a ground plane under the chip and then a >>> core >> supply >>> ring around that and a IO supply around that (C shapes, not complete >>> circle) on the bottom layer, then decoupling capacitors on the >>> bottom >> too >>> right below their respective pins. Is this feasible (college >> student, >>> just trying to save a buck on PCB manufacturing). >>> >>> Thank you, >>> James >> >> Hello James, >> This is a question with a not so simple answer. Certianly you have >> the number of signals quite low, so routing them is not a real issue. >> But you have started thinking about the real problem. Namely can you >> get the power into the chip quietly. Most modern cpus have multiple >> power pins where each pin powers a different portion of the chip. So >> sometimes when you have improper decoupling, some functions in the >> chip work while others act "dodgy." >> >> You "c" rings just may work - just pour as much copper as you can and >> provide multiple decoupling caps. However any high speed design I >> would do would have at least 4 layers. >> >> Do you really need a custom board, or can you get an eval board and >> add on your stuff - either in a breadboard region or as a daughter >> board? >> >> IHTH, >> Clay >James, I think you are going to get into trouble with a two layer pcb. You should use 4 layers. I would use 1 layer for ground and 1 for power. If there is a core voltage lower than 3.3V, I would pour that layer under the part. Often this can be the same layer as the I/O supply (3.3V). If your part uses an internal PLL for clock multiplication, you must have a very good layout. Two layers will be probably be a disaster. I use 10nF caps for most of my decoupling (0805 or 0603 SMT). Do not use leaded parts for this. I try to layout the caps around the IC so that the positive connection is close to the power pins. Make sure the ground returns go directly tho the ground plane. I also usually use a few .1uF caps for each supply. The thing to remember is there is no such thing as a capacitor. There are only devices that approximate capacitors. This is why we use different values for decoupling. Our boards separate the DSP engine from the I/O functions (two boards). You might take a look at our special promo package. This is a system based on an Analog Devices SHARC and an Altera FPGA for only $200. It comes with a built in debugger and is supported by Visual DSP. The boards work like an EZ-Kit with more flexibility. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●April 22, 20052005-04-22
"Korenje" <korenje@yahoo.co.uk> wrote in news:1113893925.156488.203920 @z14g2000cwz.googlegroups.com:> James, > > I have multiple boards with TMS320LF2406 (100pin), 2403 (64pin), 2402 > (64pin), that have only two layers and they work just fine. I use ADC, > JTAG, SPI ,CAP, EVM (PWM1-6). Also on these boards there are 6 power > MOSFETs very close to DSP. Basicly it is a BLDC controller done on 4cm > * 10cm board. Power and ground connections took some time to route. You > will have some more work to do since you need 3.3V and 1.8V supply > voltages. > > Good luck with routing > > Mitja > >I once built a two layer board with an ADI ADSP-2191. This DSP ran at about 150MHz with an input clock of 25MHz. I poured the 2.5V core carefully under the part since the core voltage supplies thge high speed stuff. I then routed the 3.3V I/O with fat traces with good ground returns. The board did not have a lot of peripherals and nothing external was fast. I poured a ground plane on the top and bottom sides of the board. I didn't skimp on decoupling capacitors, etc. Results: The board worked fine until I wanted to use the internal PLL. The PLL ran off 3.3V instead of the core. The board also failed some EMC tests for susceptability. I modified the board by just adding a 3.3V power plane and a ground plane. The board worked great!. This was the last two layer board I ever used for a DSP. I'm not saying its impossible to use two layers, I'm suggesting that the probability of success is much less than 100%. There are many pcb houses that will produce multilayer pcbs for relatively low cost in prototype quantities. Its much more expensive to get it wrong the first time. I started my engineering career as an analog guy, so I generally pay lots of attention to layout. Careful routing is important in all cases. You can't just connect the dots. I rarely use an autorouter because the router makes way too many bad decisions. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●April 22, 20052005-04-22
Reading Mr. Cotton's post and associated replies, I thought I might relate some personal experience. In the early 70's I was an EE student working a co-op assignment at a company producing what would be considered a 4-channel oscilloscope. The application was displaying EKG's with sampling <= 10's of kHZ. Part of my assignment was reviewing all aspects of the design. I was confused by the MANY ground traces that went "nowhere". I asked the senior engineer "WHY?" His essential reply was "Why use shielded cable?" There are many implications which I will leave to student ;] James Cotton wrote:> I am designing a board with a TMS320F2811 chip, and have the schematic > done. I was about to start the layout but I wanted to ask if it can work > to make a double layered board (i saw a similar thread a while back, but > it didn't seem to answer this directly). I am only going to be using the > SCI pins and the analog inputs, so routing should be feasible. I was > thinking about laying a ground plane under the chip and then a core supply > ring around that and a IO supply around that (C shapes, not complete > circle) on the bottom layer, then decoupling capacitors on the bottom too > right below their respective pins. Is this feasible (college student, > just trying to save a buck on PCB manufacturing). > > Thank you, > James
