The zero-order hold

Started by May 14, 2018
Text books are filled with info on the DAC zero order hold and it appears on the
internet everywhere. Basically its TF is (1-exp(-sT))/s where T i sampling interval.
Usually they take 1-z^-1 in cascade with the system transfer function and 1/s is
merged into the system. If the system is G(s) then they convert (1/s)G(s) to the z
domain.

Doesn't this seem a little old fashioned nowadays. I am led to believe this was the
case when we couldn't sample 10 times the highest frequency of interest, but my
experience is that the ZOH is of little consequence at high sampling frequencies
(though it does contribute a delay of course, but there is an inherent one step
delay in any digital system anyway). Added to this, who uses a DAC within a loop
nowadays in the electrical field anyway. Usually we have an H bridge and nobody
appears to have worked out what its effect is ie TF. I assume it is negligable at
high sampling frequencies too.
Already a thread on this. Tim Wescott's answer explains it well.

https://www.dsprelated.com/showthread/comp.dsp/364996-1.php