Jim Thomas wrote:> Rick Lyons wrote:>> Hi Martin, >> just out of curiosity, what does >> >> "Quidquid latine dictum sit, altum viditur." >> >> mean in English? > > "Whatever is said in Latin, seems profound." > > But I prefer "Quidquid latine dictum sit, altum sonatur" which > means "Whatever is said in Latin, sounds profound."I've occasionally considered changing to "Quidquid latine scriptum sit, altum viditur" but never have, for some reason. What do you think? Martin -- Teach a man to make fire, and he will be warm for a day. Set a man on fire, and he will be warm for the rest of his life. --John A. Hrastar
CIC Group Delay
Started by ●October 12, 2005
Reply by ●October 20, 20052005-10-20
Reply by ●October 20, 20052005-10-20
Martin Eisenberg wrote:> I've occasionally considered changing to "Quidquid latine scriptum > sit, altum viditur" but never have, for some reason. What do you > think?I like it! I wish I knew enough Latin to be dangerous rather than only slighty un-ignorant (or to use bad Latin, a non-ignoramus). A friend of mine has a t-shirt that says "It's all fun and games until someone loses an eye" except of course, that it's written in Latin. I don't remember the Latin, and I could not even BEGIN to translate it. -- Jim Thomas Principal Applications Engineer Bittware, Inc jthomas@bittware.com http://www.bittware.com (603) 226-0404 x536 Never ascribe to malice that which is adequately explained by incompetence. - Napoleon Bonaparte
Reply by ●October 20, 20052005-10-20
Jim, Looks like this topic has received many replies. Here is my view: The CIC architecture is just a computationally efficient implementation of a boxcar FIR filter. If you have a 5 stage CIC then you have 5 convolved boxcar filters. The amount of interpolation or decimation is the length of the boxcar. Here is a simple octave/matlab example: K=10; % amount of interpolation/decimation N=5; % number of stages taps = ones(1,K); for t=1:N taps = conv(taps,ones(1,K)); end plot(taps); Michael
Reply by ●October 21, 20052005-10-21
Rick Lyons wrote:> On Fri, 14 Oct 2005 11:10:01 -0400, Jerry Avins <jya@ieee.org> wrote: > > >>Randy Yates wrote: >> >>>It's a damn good article - one of the best I've ever read within the >>>class of engineering magazine articles. >> >>Hear, hear! I found a typesetting error, though. Somewhere near the >>bottom, F_s turned into >_s. I figures it out, though! :-) >> >>Jerry > > > Hi Jerry, > > yea, I see that typo now. That ">_s" is supposed > to be "Fs,in" where the "s,in" characters are > subscripted. My original manuscript didn't have > that error. (It makes me think that all italicized > characters in a manuscript must be "re-typed" > by some magazine production person.) > > See Ya', > [-Rick-] >Quick note on the hardware implementation of cic's. In interpolation, you do not need the center differentiator/integrator, it can be replaced with a ZOH and have identical functionality. I know that's true for D=1, have not looked at D >1. Also, in decimation the center stage can be replaced with a resettable integrator and get rid of the diff. stage for hardware savings. Tim
Reply by ●October 27, 20052005-10-27
On Fri, 21 Oct 2005 11:31:12 -0400, ETS <emale80919@yahoo.com> wrote: (snipped)> >Quick note on the hardware implementation of cic's. In interpolation, >you do not need the center differentiator/integrator, it can be replaced >with a ZOH and have identical functionality. I know that's true for >D=1, have not looked at D >1. > >Also, in decimation the center stage can be replaced with a resettable >integrator and get rid of the diff. stage for hardware savings. > >TimHi Tim, darn, I'm afraid I don't follow you here. Is there some website where I can go to learn more about this "zero-order hold method to reduce CIC filter hardware "idea? Thanks, [-Rick-]
Reply by ●October 28, 20052005-10-28
Rick Lyons wrote:> On Fri, 21 Oct 2005 11:31:12 -0400, ETS <emale80919@yahoo.com> wrote: > > (snipped) > > >>Quick note on the hardware implementation of cic's. In interpolation, >>you do not need the center differentiator/integrator, it can be replaced >>with a ZOH and have identical functionality. I know that's true for >>D=1, have not looked at D >1. >> >>Also, in decimation the center stage can be replaced with a resettable >>integrator and get rid of the diff. stage for hardware savings. >> >>Tim > > > Hi Tim, > > darn, I'm afraid I don't follow you here. > Is there some website where I can go to > learn more about this "zero-order hold > method to reduce CIC filter hardware "idea? > > Thanks, > [-Rick-] >Hmmm.. not sure about a web page, but look at it like this for a second order Cic interpolator: -> C -> C -> Zero stuff -> I -> I Is equivalent to -> C -> ZOH -> I The reason is the comb, zero stuff, integrate makes a zero order hold. Since the integrators are running at R times the comb rate, you just hold the data going into the integrator and you get your ZOH for free. ex: put an impulse into the center C -> zero stuff -> I that upsamples by 3 Input: [0 0 0 0 1 0 0 0 0] Comb output: [0 0 0 0 1 -1 0 0 0] zero stuff: [0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 -1 0 0 0 0 0 0 0 0] Integrate: [0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0] You can see the response is a ZOH, which is exactly the same thing you get by samping the input sequence wrt the high side clock. So, the whole center section basically is removed with no functionality loss. One of those rare instances where you get something for nothing. Take a look at this and I'll post for the decimator, it's a little different and the savings isn't as good, but it still save some hardware. Tim
Reply by ●October 28, 20052005-10-28
On Fri, 28 Oct 2005 13:22:46 -0400, ETS <emale80919@yahoo.com> wrote:>Rick Lyons wrote: >> On Fri, 21 Oct 2005 11:31:12 -0400, ETS <emale80919@yahoo.com> wrote: >> >> (snipped) >> >> >>>Quick note on the hardware implementation of cic's. In interpolation, >>>you do not need the center differentiator/integrator, it can be replaced >>>with a ZOH and have identical functionality. I know that's true for >>>D=1, have not looked at D >1. >>> >>>Also, in decimation the center stage can be replaced with a resettable >>>integrator and get rid of the diff. stage for hardware savings. >>> >>>Tim >> >> >> Hi Tim, >> >> darn, I'm afraid I don't follow you here. >> Is there some website where I can go to >> learn more about this "zero-order hold >> method to reduce CIC filter hardware "idea? >> >> Thanks, >> [-Rick-] >> >Hmmm.. not sure about a web page, but look at it like this for a >second order Cic interpolator: > > > -> C -> C -> Zero stuff -> I -> I >Is equivalent to > -> C -> ZOH -> I > >The reason is the comb, zero stuff, integrate makes a zero order hold. >Since the integrators are running at R times the comb rate, you just >hold the data going into the integrator and you get your ZOH for free. > >ex: put an impulse into the center C -> zero stuff -> I >that upsamples by 3 > >Input: [0 0 0 0 1 0 0 0 0] >Comb output: [0 0 0 0 1 -1 0 0 0] >zero stuff: [0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 -1 0 0 0 0 0 0 0 0] >Integrate: [0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0] > >You can see the response is a ZOH, which is exactly the same thing >you get by samping the input sequence wrt the high side clock. >So, the whole center section basically is removed with no functionality >loss. One of those rare instances where you get something for nothing. > >Take a look at this and I'll post for the decimator, it's a little >different and the savings isn't as good, but it still save some hardware. > > >TimHi Tim, Thanks for the reply. I'll print out your post here and have a careful look at it in the next few days. Thanks again, [-Rick-]
