Control of modulator blocks

Hi,

I am designing an 802.11b transceiver and after developing the block of
modulators and scrambler I have a question: these ones (blocks) have
control inputs which must be used to control their functionality ...
How can I control them? :

         There are three parts on the frame: preamble, header and data
... and each one can be transmitted with different modulation so ...
how can the physical layer know when it must change the modulation? ...
using, for example, a finite state machine? ... a microprocessor? ...
an embedded microprocessor?.

Thanks for your advices.

Jajo.

jajo wrote:
> Hi,
> 
> I am designing an 802.11b transceiver and after developing the block of
> modulators and scrambler I have a question: these ones (blocks) have
> control inputs which must be used to control their functionality ...
> How can I control them? :
> 
>          There are three parts on the frame: preamble, header and data
> ... and each one can be transmitted with different modulation so ...
> how can the physical layer know when it must change the modulation? ...
> using, for example, a finite state machine? ... a microprocessor? ...
> an embedded microprocessor?.
> 
> Thanks for your advices.
> 
> Jajo.
> 
I would expect that such control would come from the link layer.  As far 
as the technology to implement them -- what makes the most sense?  The 
answer to this question will depend on the required reaction speed, and 
whether you have any existing plans on where you're going to put the 
link layer.

I suspect that your speeds are great enough, and the requirements for 
the different modulation formats are simple enough, that implementing 
this as a state machine in your digital hardware would be the most 
appropriate -- but you may find that for some screwy reason it makes 
more sense to time or bit-bang this from a microprocessor.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

> >
> I would expect that such control would come from the link layer.  As far
> as the technology to implement them -- what makes the most sense?  The
> answer to this question will depend on the required reaction speed, and
> whether you have any existing plans on where you're going to put the
> link layer.
>
> I suspect that your speeds are great enough, and the requirements for
> the different modulation formats are simple enough, that implementing
> this as a state machine in your digital hardware would be the most
> appropriate -- but you may find that for some screwy reason it makes
> more sense to time or bit-bang this from a microprocessor.
>

Hi,

I agree with your opinions but I would like to point out something. My
first idea consisted on using an state machine but I noticed that this
option y the least flexible. So I found three options more: a embedded
microprocessor into the FPGA (picoblaze, microblaze or powerpc for
Xilinx FPGAs), and external microcontroller or use a PC. I am not sure
about which options is the best, what do you think? .

My problem is the speed of each deviced since, for example, an DBPSK
modulation requires a rate of 1Mbps ... At this moment, I am a bit
lost.

Thanks

Jajo

jajo wrote:

>>I would expect that such control would come from the link layer.  As far
>>as the technology to implement them -- what makes the most sense?  The
>>answer to this question will depend on the required reaction speed, and
>>whether you have any existing plans on where you're going to put the
>>link layer.
>>
>>I suspect that your speeds are great enough, and the requirements for
>>the different modulation formats are simple enough, that implementing
>>this as a state machine in your digital hardware would be the most
>>appropriate -- but you may find that for some screwy reason it makes
>>more sense to time or bit-bang this from a microprocessor.
>>
> 
> 
> Hi,
> 
> I agree with your opinions but I would like to point out something. My
> first idea consisted on using an state machine but I noticed that this
> option y the least flexible. So I found three options more: a embedded
> microprocessor into the FPGA (picoblaze, microblaze or powerpc for
> Xilinx FPGAs), and external microcontroller or use a PC. I am not sure
> about which options is the best, what do you think? .
> 
> My problem is the speed of each deviced since, for example, an DBPSK
> modulation requires a rate of 1Mbps ... At this moment, I am a bit
> lost.
> 
Microprocessor + program = finite state machine.  It's just that 
software can easily house much bigger finite state machines than a 'pure 
logic' implementation can.

So the question shouldn't be "can I write a finite state machine in 
Verilog (or VHDL) that's big enough to work?" but "will my great big 
finite state machine fit on an economical device?".

I'm not familiar with the protocol, but I bet that if you dig a bit 
you'll find that you don't need a lot of flexibility.  I would expect 
that the preamble and header are always the same length, and the length 
of the data will be known before the packet is sent.  Even if the 
preamble and header are of varying length, too, you should be able to 
put a state machine in logic that uses numbers supplied to it by 
software, then calculate the lengths of your pieces in software before 
the packet is sent.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html