Early/Late gate synchronization for QPSK signal

Hello,

I would like to know how to make a bit synchronizer for QPSK
demodulation using an Early / Late Gate Synchronization ?

I have an early / late gate synchronizer which works only  on a real
signal (NRZ data input) and not on a complex signal (I and Q)

Is the Early / Late gate can synchronize with an IQ signal (QPSK,
8PSK, 16QAM... ) ?

thanks

<fpga.vhdl.designer@gmail.com> wrote in message
news:1188996968.631632.268490@k79g2000hse.googlegroups.com...
> Hello,
>
> I would like to know how to make a bit synchronizer for QPSK
> demodulation using an Early / Late Gate Synchronization ?

E = (z0 - z2)*z1

> I have an early / late gate synchronizer which works only  on a real
> signal (NRZ data input) and not on a complex signal (I and Q)

Same thing.

> Is the Early / Late gate can synchronize with an IQ signal (QPSK,
> 8PSK, 16QAM... ) ?

Same thing.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com

You want to says : I(j-0.5)*(I(j)-I(j-1)) for I branch and same for Q
branch and then theses two resulots added

Isn't it Gardner synchronization ?

thanks

when I compute I (j-0.5) * ( I (j) - I (j-1)) do I need to add a
CLK_2x delay to I (j-0.5) to have I (j-0.5) AND ( I (j) - I (j-1) in
phase because I have a computation time of CLK_2x to compute the
substraction ?

CLK_2x is the clock which is the double of symbol clock recovered

thanks