Low Standby Current DSP

Un bel giorno Steve4DSP digit�:

> I should say at this point that i intend to process audio and sample at
> 10kHz at least 2 ADC's and 2 DAC's concurrently... 
> That said, i intend to apply the adaptive echo cancellation to the 2 ADC
> inputs
> Maybe that would help for a mips estimation...

With FPGAs everything has to do with the number of gates used; Xilinx (the
brand I'm more familiar with) has a very precise power simulator, I suppose
that Actel has one too. Of course, you will have to extimate how much gates
you need; searching between the www.opencores.net projects can give you an
idea.

> If your processing ADC/DAC IO's on an FPGA im presuming that you would
> have to interface to them externally via an SPI or whatever?

Yes, but you won't find a 100-MIPS DSP with internal DACs either, so this
doesn't make much difference anyway. :-)

Actually you could syntesize as many ADCs and DACs you want with an FPGA
and few external components, by using PWM and/or sigma-delta architecture.
You can find some interesting app notes in Xilinx site, IIRC.

P.S. Here they are:

http://www.xilinx.com/bvdocs/appnotes/xapp155.pdf
http://www.xilinx.com/bvdocs/appnotes/xapp154.pdf

-- 
emboliaschizoide.splinder.com

On Sep 18, 7:37 pm, "Steve4DSP" <stephen_lea...@hotmail.com> wrote:
> Vladimir,
>
> Thanks for your post,
>
> Point taken about the DAC not being integrated, but i dont believe thats
> the case for ADC's.
>
> 50 Mips sounds about right to me, from my rough calculations 100 Mips
> would have easily done the job.
>
> Regarding Standby Power, and Powerdown, I'm still wanting to be able to
> wake it up by a GPIO interrupt of some sort (ie, from a keypad scan), so
> it still must be awake in some respects,
>
> Given this point,
> ADSP-B531   - Exceeds the 10mA by a further 10mA in low power operation
> TMS55xx     - Exceeds the 50uA by a further 50uA in sleep with IO Active
>
> Thanks for you advice.
>
> Regards,
> Stephen Leahey

As others have said, your active power requirements are never going to
be met. You're not going to find any current processor that does ~100
MIPS at less than 10 mA. Also, you're probably best served by
specifying your power requirements in watts, not amperes. The required
core voltage can vary significantly among different parts (maybe 1.1
to 2.0 V or so), and you want an apples-to-apples comparison.

Jason

On Sep 18, 2:41 pm, "Steve4DSP" <stephen_lea...@hotmail.com> wrote:
> >> - No more than 10mA under load conditions
> At a guess i would have said that 100Mips would make the cut easily,

Depending on voltage, what you are asking for is about
4 to 8 "Mips"/mW, which is likely just above what
general purpose processors are capable of these days.

Dedicated logic for your processing algorithm, either
an ASIC or a low-power FPGA, might be one way to get
a higher MOPs/mW, by trading off against generality.
Generality (e.g. charging and discharging those wires
and gate inputs optionally usable by other operations
than the ones your specific app needs) costs power.


IMHO. YMMV.
--
rhn A.T nicholson d.0.t C-o-M