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Can anyone tell what is the general BER obtained when using a DUC and a DDC in the system?

Started by amitjonak 3 months ago12 replieslatest reply 1 month ago83 views

Hello,

I am trying to build a wideband frequency hopping OFDM system on Simulink. My OFDM system, along with subcarrier interleaving works fine otherwise. The problem arises when I include a DUC and a DDC block into my system. My idea is to use DUC and DDC to digitally hop to different bands and achieve wideband frequency hopping. I get correct spectrums and I achieve correct frequency translation too. However, the BER degrades significantly. In order to know what is happening, I tried simulating a simple BPSK system and use a DUC to digitally upconvert and a DDC to digitally downconvert and demodulate it to check the BER of the system. But I get the same high BER problem. I even tried to look for the values before and after the DUC, through which I came to know that the DDC is decimating incorrect values. Can anyone please tell what might be the problem here? And what BER values generally one can get when using DUC and a DDC. Thank you!

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Reply by dudelsoundMarch 5, 2020

Hi

I cannot help you improve your problem, but I can tell you that using up-conversion or downconversion, your BER should not change at all (at least not significantly). One thing of course: You need to band-pass filter your signal before down-conversion. If you don't do it and your signal contains energy outside your frequency band of interest, this energy will fold back into your down-sampled signal creating all sorts of trouble...

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Reply by amitjonakMarch 5, 2020

I see, the problem is with the built-in DUC and the DDC block of simulink. All it says is that they do interpolation and decimation at 3 stages with the help of CIC filters. Hence, I am thinking of making my own block for DUC and DDC since the built-in blocks have many non-tunable properties. 


The problem lies with the values after the DUC and the DDC. I tried saving the values before and after DUC and the DDC in workspace. For example, if my input frame length is 10 and interpolation factor is 4. The total length after the DUC will be 40 in that case. And when I try to look at every 4th value, and compare it with the BPSK symbols, it is very much different considering the fact that the I and Q components.get.multiplied by cos and sine values.respectively. Now, the DDC also works in a reverse order and multiplies again with the oscillator, followed by 3-stage decimation to give out the complex baseband signal. Now, here the complex baseband values that is going to.the BPSK demodulator is different than what being sent to.the DUC because of which I am.getting wrong bit values at the receiver. This makes my BER very poor. 

Hence, I would be grateful if you could please go through the block.design of the DUC and the DDC. If you are successful in achieving correct reception of bits using the DUC and DDC for a very basic transceiver system with basic specs, do let me know. Thank you!

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Reply by amitjonakMarch 15, 2020

Can you please refer to my new question in the link given below? I have specified clearly about my problems with diagrams.

https://www.dsprelated.com/thread/10597/help-in-designing-filter-for-duc-digital-up-converter-and-ddc-digital-down-converter-using-the-built-in-duc-and-ddc-blocks-in-matlab-simulink


Thank you!

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Reply by kazMarch 5, 2020

I agree with dudelsound that upconversion/downconversion if done correctly should not affect BER. UPconversion/downconversion imply frequency shifting to some point and back. upsampling/downsampling may also be involved in which case they have to be done correctly. Another issue might be to do with bit resolution across various stages.

You haven't told us what that mystery simulink upconverter/downconverter is actually doing. In particular is it aware of your signal bandwidth. And why do you do it in simulink? 

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Reply by amitjonakMarch 5, 2020

Hello! 

Well, the simulink does have an option to include the signal bandwidth. For the simple BPSK system, here are the specs that I used - 

1. Two - sided bandwidth = 2 KHz

2. Input sampling rate = 10 KHz

3. Interpolation factor = 30

4. Center frequency = 100 KHz

If not simulink, what do you suggest to use? I use it since I plan to implement my system on hardware as in a RFSoC board, which has built-in DUC and DDC. If I could do that in simulation, then I can draw a comparison between software and hardware. 


The Simulink block does interpolation in 3 stages. It first passes to an interpolation stage, then a CIC compensator and then a CIC interpolator. After this, the I and Q components get multiplied by cos and sine and added to get the real bandpass signal. Now, the problem here is I cannot exactly know the value of every stage of interpolation since the block doesn't permit to do so. In that case, I am thinking of making my own block. But, I can't understand what is causing the bits to get corrupted when I obtain the correct spectrums. 



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Reply by kazMarch 6, 2020

One alternative is to model DUC/DDC using matlab code. You will need very few statements such as one or two for mixing up/dn, filters for interpolation/decimation and full control over bit resolution and full visibility. 

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Reply by amitjonakMarch 15, 2020

Can you please refer to my new question in the link given below? I have specified clearly about my problems with diagrams.

https://www.dsprelated.com/thread/10597/help-in-designing-filter-for-duc-digital-up-converter-and-ddc-digital-down-converter-using-the-built-in-duc-and-ddc-blocks-in-matlab-simulink


Thank you!

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Reply by amitjonakMarch 15, 2020

Can you please refer to my new question in the link given below? I have specified clearly about my problems with diagrams.

https://www.dsprelated.com/thread/10597/help-in-designing-filter-for-duc-digital-up-converter-and-ddc-digital-down-converter-using-the-built-in-duc-and-ddc-blocks-in-matlab-simulink


Thank you!

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Reply by amitjonakMarch 15, 2020

Can you please refer to my new question in the link given below? I have specified clearly about my problems with diagrams.

https://www.dsprelated.com/thread/10597/help-in-designing-filter-for-duc-digital-up-converter-and-ddc-digital-down-converter-using-the-built-in-duc-and-ddc-blocks-in-matlab-simulink


Thank you!

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Reply by amitjonakMarch 15, 2020

Please refer to my new question which is much more detailed. The question has all the necessary specs details along with several screenshots of the block, spectrums, and filter responses. Thank you!


https://www.dsprelated.com/thread/10597/help-in-designing-filter-for-duc-digital-up-converter-and-ddc-digital-down-converter-using-the-built-in-duc-and-ddc-blocks-in-matlab-simulink

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Reply by kazMarch 15, 2020

I don't see any shaping filter in your simulink model. 

You need to have a shaping filter in DUC followed by matched filter in DDC

Then at receiver when you decimate you need to pick which sample phase is best.

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Reply by jimelectrApril 21, 2020

I assume you have a legitimate copy of Simulink.  If so, this may be a question for the folks at MathWorks.  It is possible that their DDC and/or DUC models are flawed or you are not using them as intended.  It would be good to rule those out.