How to compute a phase? [phase estimation]

Started by Aida92 4 weeks ago10 replieslatest reply 2 weeks ago136 views

i am working on a signal under low SNR and have to correct a phase.

Aktuell I am looking for a n algorithm how to estimate a phase. In implemented algorithm I am using the symbol/sample with max energy.

**Question 1**

Can i compute a sample with max energy by using the correlation between I and Q?


Input or Received signal model ( Rx): BPSK signal, which was upsampled with a factor 8 and filtered with the raised cosine filter. Signal has a phase offset, but it is not constant. Signal is transmitted via a channel, i.e. a noise is added.

The receiver loop looks as follow:

1. CORDIC rotation mode rotates each sample in a symbol. Start angle (Phi_0)is 0.

x_k – is a sample

x_k_hat -rotated sample

2. After CORDIC, amplitude (A = sqrt(real^2 +imag^2^)) and phase (Phi = atan real/imag) are computed. The amplitude of the symbol is computed as sum and found the sample with max amplitude.

3. Calculate the difference between the current sample and its directly adjacent left-hand neighbor: dPhi

If the difference between the two is larger than +π, then subtract 2π from this sample

If the difference between the two is smaller than -π, then add 2π to this sample

4. Compute for the whole symbol: sum of dPhi

5. Compute average amplitude and phase using the sample with max energy [corresponds to the middle of the symbol ( I hope)]

6 take a difference between averaged phase and Phi_0. The resultant will be used to update Phi_0.

PS My next steps is demodulation

**Question 2**

I have corrected a phase shift, how to correct time offset?

i need to add a timing recovery loop. Should i use the rotated vectors?

DOes anyone have an example for BPSK?

**Question 3**

What is a demodulator step in PLL?

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Reply by SlartibartfastMarch 25, 2021

Usually synchronization of both timing and phase are done with feedback control loops.  Usually timing is synchronized first so that phase can be synchronized using the symbol sample rather than inter-symbol transition samples.  

One big advantage of using control loops is that the loop bandwidth and damping ratio can be controlled for performance optimization.   The loop bandwidths are typically fairly narrow in order to provide a lot of averaging and filtering over multiple symbols to reduce the effects of noise and interference and sometimes the modulation effects as well.

I'm not quite sure what you're asking in question #1, but I think the answer is no.

For question 2, it is better to synchronize timing first, then phase using the symbol sample selected by the timing recovery system.

For question 3, I'm not sure what you're asking, but a PLL is typically the feedback control loop used for recovering both timing and phase synchronization.

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Reply by Aida92March 30, 2021

Hello Slartibartfast!

could you please provide more details what feedback control loops are? did you mean PLL?

[ - ]
Reply by SlartibartfastMarch 30, 2021

Yes, a PLL is a feedback control loop.   Usually the loop architecture and development use something like a 2nd order loop filter, which is the same 2nd order loop filter used in any control system and uses the same design techniques, etc.

Here's a basic treatment, and there are a number of books that are good references.   Gardner's book is cited in the presentation.

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Reply by Aida92April 1, 2021

Hello Slartibartfast!

thank you for your suggestion.

I have checked and PLL doesn't work for my scenario. If the Doppler frequency is big, data rate is low.. and delta frequency small...

Are there other algorithms which I can use to correct phase and frequency?

PS Costas loop I checked too

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Reply by SlartibartfastApril 1, 2021

Well, requirements matter, and you haven't really stated any, so it's hard to say what would work for you or not work.

In many systems frequency offset is removed first, during acquisition, and then the PLL started.  A PLL can track out doppler within certain limits, but you seem to have unstated requirements, so I can't provide any useful details.

If it is something like a mobile system with a lot of multipath and crazy doppler, if a PLL really can't be made to work then you may need to do differential detection instead.

Even in the presence of crazy doppler and multipath, a PLL is generally still used to recover the symbol timing.

This assumes that when you said "BPSK" you meant single-carrier BPSK and not OFDM or FH or something.

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Reply by Aida92April 6, 2021

i study satellite communication and working on a test signal with big offset. Probably I have something additional to PLL?

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Reply by SlartibartfastApril 6, 2021

For satellite communications Doppler and multipath are generally not big problems, at least not compared to many terrestrial applications.   Usually the frequency offset is detected and removed first, and then separate PLLs used to lock timing and phase.   Timing usually locks first.  The phase PLL can be designed with the assumption that the timing is locked.

Removing large frequency offset is a separate task, and there are many different ways to do it depending on the circumstances (how much adjacent energy, channel spacing, etc.)

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Reply by PlatybelMarch 25, 2021

Hello Aida92: Readers of DSPR come from a variety of backgrounds.  It will help someone to answer your questions if you provided more details.  I have no expertise for Questions 2 and 3, but maybe able to help for Question 1, if I can understand the problem.  Please describe (and provide a plot) of your input, and the program.

Please explain atan(Q/I) = phi and energy.


(for the curious, Playtbel is short for Platybelodon, an extinct species of the elephant family, known only from fossils).

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Reply by napiermMarch 25, 2021

There is a lot going on.  It's hard to break the problem up w/o going into the background details first.

The best nuts and bolts book I've seen is by Michael Rice.

Do this in a google search:

"michael rice digital communications a discrete-time approach pdf"

The book is available in paperback for not too much money.  It is written for undergraduate students so it is very approachable.

Well Drat!  Just tried myself.  The soft copy isn't to be found and even from Abe Books the price is silly.  It's out of print so suddenly expensive.

He republished it himself.  $60 on Amazon Prime.

  • Publisher : Independently published (August 28, 2020)
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Reply by Mannai_MuraliMarch 26, 2021

In genral receiver will have carrier frequency offset not only mere phae offset.You may have to correct for difference in frequency and phase of DAC (At Transmitter),ADC (Receiver) Sampling clocks.

If the frequency offset is less than 10 percent of symbol rate we can correct first tiing followed by carrier phase/frequency.Reason is the carrier loop will run at symbol rate and not sample rate and hence savings in computation.

But if the freqyncy offset is more than 10 percent of symbol rate we can NOT do timing first.We have to do either joing timing and carrier loop or correct the frequency offset first.You may refer Digital Communication Receivers Vol2,1990 by Meyr.

We can use either Non Data Aided(NDA) or Data Aided (DA) Algorithms.For timing we can have differentiator and interpolator and loop filters,NCO for PLL.We can use either polynomial interpolator or MMSE (Truncated sinc) Interpolator.MMSE will give better performence.

If you want more details please EMail me.I can share some of my codes.