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choose the antialiasing filter

Started by gabrics 3 years ago8 replieslatest reply 3 years ago183 views
Hi, i'm new to signal processing. I probably have not understood properly the following topic: i'm trying to use the XADC analog to digital converter on my FPGA. It's a switched capacitor ADC manufactured from XILINX with 1 MSPS and 12 bit resolution.I'm dealing with sampling of very noisy signals so i started to think about the spec of the antialiasing filter. The guide provided by XILINX says that there's a settling time that has to be met (500 ns) and gives an example of designing a single pole filter to meet the time constrains of the ADC. I do not have a specific bandwidth for the signal to be sampled but i want to use as much as i can related to my application. I hope to obtain a good resolution of at least 10 bit.

My requirements are (i think) : a low pass filter with a corner frequency of something around 100KHz and a 500 Khz(half of Nyquist) gain of at least -40 DB. In every datasheet that i read i cannot find the settling time information to understand if it's good for my application. Can someone help me to understand where to find that value? Thank you everyone.

https://www.analog.com/media/en/technical-document...

https://www.analog.com/media/en/technical-document...

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Reply by Joe_WestNovember 18, 2018

You state that you want 40db of attenuation at half the sampling rate. That is one part in 100 of voltage. Yet you also state that you want 10-bits of resolution. That is about one part in 1000, so there's a factor of 10 missing somewhere. I suspect you really need 60db of attenuation for frequencies higher than sample-rate/2 

How much signal bandwidth do you really need to capture? That would establish the lowest pass-band frequency of your LPF, and combined with your aliasing requirements would thereby determine how many poles of (analog) LPF you need as well as the settling time of the LPF.

Something you might find helpful to read <https://www.eetimes.com/document.asp?doc_id=127232...> as it gives a not-unreasonable introduction to the settling time issue.

See if that is of any help.

Joe



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Reply by gabricsNovember 18, 2018

Thank you for the reply. I agree with you about the attenuation, and thanks for the suggestion. I'm not really interested in how much bandwidth to capture i just want to learn two things : drive the XADC properly and choose a good(bessel) low pass filter from the lists of manufactured one. So the design is concerned first of all with these requirements. After choosing the filter i can say, ok this project can handle frequency up to ...HZ with 10 bit accuracy. I have already read the article that you post and i've surely understood the settling time issue in my case but i cannot find this information on the datasheet. So assuming your suggestion about the attenuation i'm not sure if the time constrains will be met. Thank you very much for the answer.

Gab

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Reply by Joe_WestNovember 18, 2018

The 500ns settling time of the ADC is what is required for full 12-bits of resolution to a full-range step input. (Resolution doesn't address things like ADC linearity however). Since you "only" need 10-bits of resolution (and accuracy?) you can relax the ADC settling-time requirement quite a bit, at least a factor of four I suspect (I'm not doing any calculations here, so check it yourself).

Do the data sheets for the manufactured Bessel filters give any settling time information? And if so, settling to what percent of final value? I suppose you could model the Bessel filters and see what the result is, presuming that the filters don't have any non-linearities due to e.g. saturation or slew-rate limiting of some internal gain stage.

Good luck,

Joe

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Reply by gabricsNovember 18, 2018

The 10 bit resolution is the minimum that i can accept. The only missing information is the settling time on the datasheet, i don't understand if i cannot see it or if there's not at all. So i cannot say also where i want the value to settle(obviously a value that gives me at least 10 bit). Thank you again for the suggestions.


Gab

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Reply by pomartelNovember 19, 2018

Reviewing the app note for the XADC, https://www.xilinx.com/support/documentation/appli...

they are assuming that the input to the XADC is an RC circuit with the internal multiplexer resistance 100 Ohms and the sampling capacitance 3 pF.  Can you estimate what the effective resistance of the output of your filter?  The stray capacitance of the circuit board?  You could use these to come up with a time constant for the circuit, but what you need to do is make sure the voltage at Csample (figure 1) is stable.

Settling time is not really a property of an analog filter.  Just make sure the output of the filter, or a buffer amplifier if you need it, is able to provide enough current to charge Csample in a timely fashion.  From a practical point of view, I don't think you will have any problem with the system you describe

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Reply by gabricsNovember 27, 2018

thanks for the suggestions, i will try it. 


Gab

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Reply by shafie7November 19, 2018

Although the datasheet does not refer directly to settling time, there are other parameters which are function of it.

  • ADC has high input impedance, say 1KOhms, and the Thermal noise is kT/C, where k, T, and C are Boltzman constant, Temperature I K, and capacitor in Farad.The datasheet specifies the input referred Thermal Noise in uVrms, sqrt(kT/C).So you can calculate C, therefore, RC time constant, hence settling time.
  • Given the highest operating input frequency of the ADC, you can say that ADC will be functioning and meeting the performance for those frequencies up to spec.Anyway, time and frequency are inversely proportional.Therefore T = 1/f, for highest frequency could be the settling time.
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Reply by gabricsNovember 27, 2018

ok,thank you very much. 


Gab