SDR Direct-RF User Symbol Rate

Started by ees3dc 4 years ago11 replieslatest reply 4 years ago176 views

I'm wondering how to decouple user data/symbol rate from a carrier clock in a Direct-RF DAC transmitter solution.

I have an I+Q root raised cosine data source that I can "multiply" by xoring I,Q with a SIN/COS (0,0,1,1)(0,1,1,0)  bit and then sum. This modulation method is actually really simple to create in logic as there is no NCO, just xor "multipliers"/inverters and a single I+Q sum. This method works on the bench but it locks the symbol rate to the IF frequency and the DAC clock: (IF=fDAC/4 and user rate = IF/4) So my user rate can be no greater than fDAC/16. I believe this is how mobile phones modulate a signal

This works just fine if I want to generate a modulated carrier at say 400 MHz at the DAC and then I use a mixer with LO to hit the desired RF frequency of say 8.2xxxx GHz.

Now I want to get rid of the IF/mixer stage and go Direct-RF. I have to clock the DAC at a particular frequency so that the nth image signal appears exactly where I want it. But with my "locked" symbol rate/fDAC, I can only generate particular user data rates.In an end to end system this is not a good solution because I'm unlikely to be able to set the demodulator to these "unique" user symbol rates. And its going to change depending on the frequency allocated. This is clearly not a good design.

So I'm left wondering how I can effectively "cross clock domain" from my IQ symbol rate (user defined) to a desired carrier frequency (final RF carrier frequency defined). What does not help is I need to generate high symbol rates (200 MSym/s).

Hope that makes sense!! 

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Reply by kazDecember 30, 2018

I suggest using variable rate converter that accepts any data rate but outputs at DAC rate

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Reply by fred_harrisDecember 30, 2018


The standard approach is to use the sqrt Nyquist filter for two tasks: the first is to perform the spectral and temporal shaping and the second is to perform an up-sampling from symbol rate to baseband sample rate. I, as do many others, use 4-samples per symbol.

The sample rate change is performed by a 4-path polyphase partition of the shaping filter. This partition has 4-outputs for each input. Following the shaping we use a second filter to preserve the spectral shape but raise the sample rate. This is traditionally performed in a second polyphase filter. I like to use a 32 path polyphase filter to perform arbitrary resampling. This filter can interpolate by any arbitrary rational ratio with spectral artifacts about 50 dB below full signal level. I also use a second 32 path polyphase filter to perform linear interpolation, computing both y and y_dot and obtaining arbitrary interpolation with a two term Talyor series. the pair of filters support spectral artifacts about 90 dB below full scale.

The output of the second filter can then be up converted to any arbitrary center frequency to form a digital IF signal which requires only a single DAC and band-pass filter to form the analog output signal. Good design practice has us place a sin(x)/x compensating filter between the digital IF and the DAC. One useful compromise is to place the digital IF frequency at the quarter sample rate, which as you pointed out only requires the [1 0 -1 0] and [0 -1 0 1] terms for the cosine and sine translation. 

I also use polyphase filters at the receiver to perform timing synchronization

Play with the two attached matlab files...

I teach a modem design course, so I probably can can help if you need additional material.

fred harris


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Reply by ees3dcDecember 30, 2018

Thank you both for the reply. Apologies, but I should have pointed out that my I,Q outputs are already 12 bit wide root-raised cosine filtered and producing 4 samples per bit. This with my IF being fDAC/4 is where the symbol rate = fDAC/16 comes from.

Somewhere in the design there must be a crossing of clock domains (symbol rate to fDAC) and so I guess there must be some setup and hold violation. You can't just us a FIFO.

(DSP is not my forte.... So I need to research sample rate conversion I guess.


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Reply by kazDecember 30, 2018

You are mixing up between timing of registers and rate conversion. They are two different issues. You need a rate converter. Either FIR based or cic.That can be fed with rate values at input and output then you apply mixed interpolation and decimation. Google fractional rate converter(variable). The reason you mixed up is because you use the term clock crossing 

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Reply by fred_harrisDecember 30, 2018

You can follow your shaping filter output with the arbitrary interpolator and go to any sample rate you want and the heterodyne trivially to the quarter sample rate.

run my spawar_modem code to see it happen

fred harris

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Reply by SlartibartfastDecember 30, 2018

As fred mentioned, you can decouple the symbol rate and the sample rate with a polyphase resampling filter.   You will likely have to decouple the sample rate and symbol rate in the demodulator unless you have some way to steer the phase of the sample clock, which isn't an efficient design tradeoff these days.   Usually, in order to avoid the inefficiencies associated with steering the sampling clock, a polyphase resampling filter is also used in the demodulator.

There are other methods, but these days with gates and memory being relatively inexpensive, polyphase resampling filters are a very good way to decouple the symbol rate and the sample rate, both in the modulator and the demodulator.

Unfortunately, this is not a trivial area of DSP, so expect to do some studying before you fully grok it.

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Reply by fred_harrisDecember 31, 2018

Hello ee3sdc,

If you can find a copy of my book, Mulirate signal processing, I do an OK job describing the modulator structure which includes a polyphase filter for the arbitrary interpolator which decouples the symbol clock from the sample clock. The spawar_modem_2.m file illustrates how this happens. The book also describes the timing recovery loop that uses a polyphase filter to extract the time aligned samples to form the symbol rate samples using a similar arbitrary interpolator. Nowadays, every QAM modem I design uses these structures. The timing_loop_demo_2018b2.m  illustrates the demodulator process. A section of my synchronization notes is presented in this pdf file SPAWAR_2108_SYNCH_3.pdf


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Reply by ees3dcJanuary 3, 2019

Direct RF.JPG

Thanks, I will try to dig out a copy... I attach some numbers of what I'm trying to achieve

I am wanting to output from a DAC a modulated carrier at 8.2 GHz with 200 MSym/s data. I do this by band pass filtering a Nyquist image out of the DAC (the standard method).

In the FPGA my data source is an I+Q RRC pulse shaped parallel output. As its 200 MSym/s, its clock is 100 MHz, 200 MHz etc (I have some flexibility with the level of parallelism on the output).

In the FPGA I "modulate" this onto a 800 MHz carrier I have 4 (RRC interpolated) sample points per carrier. I actually have demonstrated this working end to end on the bench (but with the DAC clocked at a fixed multiple of the IF/carrier).

But now the trick is to get this 800 MHz carrier (implemented at 3.2 GSa/s with 4 samples per carrier period) being clocked by the RF-DAC at 4.5 GSa/s.

So I guess I need to rate convert 3.2 GSa/s to 4.5 GSa/s. 

But the LCM of 3.2 GHz and 4.5 GHz is 14.4 GHz. I’m not sure how you’d go about implementing such a converter. I can only achieve parallelism of 4 for for I,Q outputs.

Or perhaps some other topology..

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Reply by fred_harrisJanuary 4, 2019

The problem you have is that the center frequency you want is not in the baseband Nyquist zone. You have to access a higher Nyquist zone. The way you do this is output a sample and three zero value samples from your DAC some of the high end DACs will do this for you... you zero pack the DAC output which narrows the width of the ZOH DAC impulse response... this widens the main-lobe width of the sin(x)/x spectral width so that the first 4 Nyquist zones lie in the main lobe width of the new reduced width sin(x)/x... the Nyquist zones see the drop in amplitude due to the reduced gain of the main lobe. You extract the desired reduced amplitude Nyquist zone and take the hit on the gain reduction. Some DACS will alternate sine to zero out the DC Nyquist zone and shift the main lobe off of DC. What DAC are you using... can you send me the part number or the data sheet?

best regards,

fred harris  

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Reply by ees3dcJanuary 5, 2019

I believe the only viable DAC is the e2V EV12DS460A 7GSa/s DAC. The next fastest DAC is the AD719x series but they don't appear fast enough. I am flexible on the DAC choice.

Forgive me but yes, I agree I need a higher Nyquist image. But if I clock the DAC at 4.5 GHz, my 800 MHz carrier will appear at 800 MHz, 4500 MHz +/- 800 MHz and 9000 MHz +/- 800 MHz. So I take 9000-800 as the signal I want. I attached a diagram further up in this thread. I don't believe I need to perform any interpolation in order to access the other Nyquist images. They just appear there already(?). That is what I saw on a spectrum analyser when I was testing this concept at locked sym-IF-carrier rates.

My backup plan is to take the easy route and just output 800 MHz carrier from the DAC and use an external mixer with LO....

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Reply by kazJanuary 3, 2019

800 MHz on fpga doesn't sound right unless you are breaking signal into parallel streams. In this case rate change will get hard. I suggest you post on fpg forum as this forum is software and many processes in software are not practical for fpga at all. Software processing in one statement may take weeks in fpg