I wonder can anyone elaborate about the difference between ADPLL and linear PLL. I have implemented both version in Matlab but the loop bandwidth for the ADPLL is much higher than linear PLL and I can only tune the APLL locking capability by changing the loop bandwidth however in LPLL I can change VCO and multiplier gain and let loop bandwidth remain constant. Can anyone explain why the loop bandwidth in ADPLL is that high?

What do you mean by "ADPLL"? If you mean "all digital PLL", then there's no specific reason that the bandwidth needs to be high -- I've implemented such PLLs with fairly low bandwidths that worked just fine.

If you can, point to a paper or something.

Thanks.Can you please point me to the paper or set of parameters that let you design ADPLL with low bandwidth.

Set the loop gains low. Be done with it. It should be that simple. If there's a paper on how to do it it's a page of title sheet, a page of references, and the text is shorter than the abstract.

So there's something missing from your problem statement here, because you should be able to set your loop gain, and hence your closed-loop bandwidth, arbitrarily low.

You mention locking capability, but given equivalent phase detectors that's going to be roughly the same whether you're realizing your PLL in analog components or in all-digital.

Based on this message, and your previous ones, I think you need to get your hands on a good book on PLL design. The only one I can recommend probably won't be a big help because it's written by and for analog circuit designers (Wolavar: "Phase Locked Loop Circuit Design"). Hopefully someone can recommend one for you.

Get it, take the time to study it, ask questions if you need to.

I'll second Tim's statement that you need to be clear about what you mean. Anything you run in Matlab is digital. It may be a simulation of an analog system, but it is digital. Did you even mean analog by "linear PLL"? You need to clarify what you're asking.

Yes, ADPLL is all digital PLL and LPLL is a linear PLL or analog one. in ADPLL I am not taking the VCO and phase detector gain into the account and assume they are 1. but in LPll they are considered as a parameter.

I know everything in Matlab is digital but the main distinction between my linear PLL and ADPLL is that ADPLL assumes VCO and multiplier have gain of 1.

What are the units of the VCO gain when it is equal to 1? Which multiplier do you mean? Do you mean the phase detector? What are the units of the gain when the gain is equal to 1?

Yes, phase detector is realized as a multiplier and VCO unit is rad/Volt since output of loop filter is voltage and I will have phase at the output of VCO. phase detector gain should be rad/volt as well. When I said it is 1 is because I am not even taking them into the account. It seems that they are there.Therefore for VCO I Implemented the integrator and for phase detector only multiplier followed by gain of 1 and loop filter is PI controller.

The units of the products of the oscillator and detector gains should be something like 1/seconds. "Volts" are usually abstracted in a digital implementation, so you might want to revisit that.

I second Tim's recommendation to find a good book or reference on PLL design and learn the basics, as it seems like you've been thrashing on this for a while.

I use Gardner's "Phaselock Techniques", but it is not necessarily for beginners, and it is also developed in an analog design context. This is a short example (for dsp practicioners) of one way to apply the same design principles to a digital PLL:

http://www.compdsp.com/presentations/Jacobsen/abin...

Hello Chess,

This online webinar will be helpful to you.

PLL

https://ortenga.com/ortenga800/

Best regards,

Shahram

Thank you so much Shahram.