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Signal Generation methods and alternatives

Started by PSG_ 3 months ago7 replieslatest reply 3 months ago128 views

Hi all, 

I am doing a study in which I want to compare some different methods for signal generation and also detection.  I am trying to achieve the following:

1. Generation - I would like to generate 'N' precise sinusoids digitally and have them superimposed as a single time series of data.  N in this case can be anywhere from 1, to 10000.  The tones of interest will be produced across a bandwidth of 500MHz.  My aim for frequency resolution is to be able to generate down to 1Hz accuracy (Feel free to call this an insane set of requirements).  Currently I have used an IFFT to generate what I would like and it takes a very long time.  I would like it to be much quicker, on an FPGA ideally.  I haven't delved enough into whether or not I could achieve the outcome with CORDICs or DDS.  I am keen to know if there are perhaps better generation techniques out there and if not, is there a way I can reasonably expect to achieve these generation goals with the IFFT?  

2. Detection - I would like to receive the signal generated above, and be able to 'monitor' individual tones in real time.  I had been weighing up whether to use a bank of filters or to use a sliding DFT (or perhaps a sliding Goertzel?).  I don't have a lot of experience with the Goertzel filter, however I have read that it is less stable than a direct FFT.  Is there a way to 'stabilise' the Goertzel filter?  What might be the best way to build a scalable real-time monitor of signal tones?  As a requirement, I basically want to output an IQ sample stream for each frequency tone generated. 

I will be using an FPGA to achieve both goals above. 

Any help or suggestions are very welcome!

Best Regards,

Phil

[ - ]
Reply by chalilJuly 15, 2019

Phil, getting accuracy of 1Hz at 500MHz is difficult to achieve with cordic or LUT with interpolation. 

However, i feel, if you have wider accumulator, then following classical expressions can scale to the requirement. 

sin(x0+dx) = sin(x0).cos(dx) + cos(x0).sin(dx)

cos(x0+dx) = cos(x0).cos(dx) - sin(x0).sin(dx)

start with x0 = 0 and sindx = sin(2*pi/fs); cosdx = cos(2*pi/fs);

I realized on a DSP core with 64-bit accumulator using fixed-point case. the key is to represent cosdx and sindx. 

if you try the above expression in excel, the initial cells will look as follows:

freq =  100000000 cos sin
sample rate =  1000000000 0.628318531 0.809016994 0.587785252
0 1
0.587785252 0.809016994
0.951056516 0.309016994
0.951056516 -0.30901699
0.587785252 -0.80901699

try changing the freq by 1 Hz, the change in sindx is only in 9th digit ! so key is to take care of the fixed-point representation. 10 digits would need more than 33 bit of accuracy. so, you would want a mult at 40bits and accumulator at 80bits. 

Hope it helps

-Chalil



[ - ]
Reply by PSG_July 15, 2019

Thanks for the suggestion Chalil, do you think this more classical approach would work from a resource perspective in an FPGA environment?  For example,  generating 10000 parallel sinusoids via the classical expression would surely be resource heavy? 

Alternatively,  I suppose I could use a single sine function to generate multiple frequencies sequentially, I.e. have 100 parallel sine functions producing 100 vectors recursively and then summing them with a massive accumulator. 

Maybe I will test this out. Thanks for the suggestion! 

Phil

[ - ]
Reply by weetabixharryJuly 15, 2019

Does N change only at compile time, or at run time too?

Do the frequencies that you want to generate change only at compile time?

Could you explain a little more about what your ultimate goal is in the "Detection" part? In a significant portion of the signal processing literature, "detection" has a very specific meaning (in this context: to estimate the number N).

I would suggest that an FFT is almost certainly not the best tool for this job.

[ - ]
Reply by PSG_July 15, 2019

Ideally I would like both N and the frequencies to be run time configurable.  


For the detection side, I ultimately want to continuously observe the I and Q behaviour of each frequency,  I.e. whilst monitoring f=200MHz, be able to detect a brief phase shift on a time scale of approx.5us.  After this time the signal will return to its original phase.

Part of the difficulty is that I am trying to detect the change in an array of ultra high Q resonators.  These have Q factors of up to 100000,  with FWHM of down to 1kHz.  On top of this,  they currently can’t be manufactured exactly to the frequency spec,  so they have random frequency with each batch that are made (and each device within each batch).  I currently have cases where I need to tune with a resolution down to 100Hz.  The plan moving forward is to explore if I can go further and with more tones

Perhaps I should add a little hardware context here too.  I am currently using a Virtex 7 to control a AD9361 RF transceiver. In this particular revision of the experiment,  the specs are a little more relaxed. I have 32MSps sampling for both DAC and ADC and I would only like to achieve a 10 tone demonstration. (Generate 10 tones,  monitor these 10 tones).


I am concerned about the scalability Of going from 10 tones to 10000, so I am considering evaluating the use of a Zynq Ultrascale+ RFSoC chip along with a number of different DSP techniques.  These RFSoCs have built in ADCs and DACs which have rates of 4GSps (12 and 14 bit resolution).

Hope this helps with a bit more context.

Regards, 


Phil  

[ - ]
Reply by kazJuly 15, 2019

Hi, you didn't say anything about sampling rate and how you will achieve 1G on fpga for the 500MHz tone.

If you want to generate all 10000 tones and add them up then the way for it is iFFT (like OFDM) but a resolution of 1 Hz is too drastic. To get 10000 tones from iFFT at 1Hz you need very low sampling rate yet this will have to be high enough to achieve highest frequency. Doesn't look easy job but more details are needed.

Kaz

[ - ]
Reply by PSG_July 15, 2019

I am currently using a Virtex 7 to control a AD9361 RF transceiver. In this particular revision of the experiment,  the specs are a little more relaxed. I have 32MSps sampling for both DAC and ADC and I would only like to achieve a 10 tone demonstration. (Generate 10 tones,  monitor these 10 tones).

I am concerned about the scalability Of going from 10 tones to 10000, so I am considering evaluating the use of a Zynq Ultrascale+ RFSoC chip along with a number of different DSP techniques.  These RFSoCs have built in ADCs and DACs which have rates of 4GSps (12 and 14 bit resolution).


I am currently using an IFFT to generate the 10 tone example and it works fine,  however it has a significant load time and does not end up as run time configurable. Is there a way to generate ‘local’ high resolution frequency samples centred around individual tones and then stitch them together post-IFFT

[ - ]
Reply by kazJuly 16, 2019

In that case of few tones with resolution of 1Hz you can do this:

generate one frequency (f1) from an NCO.

generate another frequency of 1Hz.

mutliply f1 by 1Hz to produce f2.

multiply f2 by 1 Hz to get f3 ...etc

add up all after latency adjustment.

you may repeat above module as many times as practical and add up all.