Hello, I'm new in the dsp world. I am doing a project that is about an implememtation of 20-points fft in vhdl. ** where I have decomposed...

Hello, I'm new in the dsp world. I am doing a project that is about an implememtation of 20-points fft in vhdl. ** where I have decomposed N=2*2*5. I have already written radix-2 processor in vhdl but now I'm facing the problem when it is about N=5 in vhdl. I have searched a lot on google but not satisfied. Please help me how to write code in vhdl for N=5. Thanks

Hi, I am a logic designer new to the DSP area and I have a few basic questions regarding FIR/IIR filters. Any help/pointers is appreciated. ...

Hi, I am a logic designer new to the DSP area and I have a few basic questions regarding FIR/IIR filters. Any help/pointers is appreciated. I read that FIR filters have no poles , it has only zeroes. In that case, how can I design a 4-pole FIR filter? Does 4-pole, 4-tap, and 4th order filters all mean the same thing? I used an online tool to come up with the coeffiencts for a 4-pole filt...

Hello All: I am designing cic filter and compensation filter. Fs is the signal sample rate and R is the down sample rate with cic filter.I search...

Hello All: I am designing cic filter and compensation filter. Fs is the signal sample rate and R is the down sample rate with cic filter.I search most of articles about cic+compensation filter design. And most of Amplitude to Frequence feature for cic+compensation filter is shown in the Fs frequency but not Fs/R. In my understanding of cic+compensation filter, the Amplitude to Frequence feature ...

Hi! can anyone give me some hints on how to handle with the noise of DDC/DUC design implemented by CIC and FIR? I have realized the function of...

Hi! can anyone give me some hints on how to handle with the noise of DDC/DUC design implemented by CIC and FIR? I have realized the function of DDC/DUC,but it comes out that the noise power is too high for my machine,and the noise analyzed in freq has a peak in the centre of each carrier.can anyone pls help me? thanks!

Hi, I am working on power analysis of general purpose applications in Quartus-II 9.1. The Model sim was invoked for testbench simulation after...

Hi, I am working on power analysis of general purpose applications in Quartus-II 9.1. The Model sim was invoked for testbench simulation after compilation of the project in Quartuss-II by using a do script file. The vcd file was generated with do file script as shown below but when I tried to generate vcd file with testbench that reads input from input.txt and put output into output.txt file t...

Hi, I am trying to design Half Band Interpolating by 2 FIR, something that should be straight forward, however, I came across the problem that...

Hi, I am trying to design Half Band Interpolating by 2 FIR, something that should be straight forward, however, I came across the problem that raises suspicion. Since the filter I am going to use is half-band, every second coefficient is 0, and in order to perform interpolation by 2, I am adding 0's on every second place. For number of coefficients of 9, coefficients 0, 2, 4, 6 and 8 are non-ze...

1) I need a simple to code in Verilog HDL for implementing a FIR Filter. Filter equation is as under : y[n] = 1/3(x[n] + x [n-1] + x[n-2] 2)...

1) I need a simple to code in Verilog HDL for implementing a FIR Filter. Filter equation is as under : y[n] = 1/3(x[n] + x [n-1] + x[n-2] 2) Is there any book availaible for implementing DSPs in Verilog HDL.. Thanks

Hello ! I am beginner with FPGA. I started with ISE 11 Web pack and Spartan 3A Dsp 3400. I try to make some simple projects but i...

Hello ! I am beginner with FPGA. I started with ISE 11 Web pack and Spartan 3A Dsp 3400. I try to make some simple projects but i realized that I have problems with clock signals. At the beginning I used Single DCM_SP from IP CORES to create clock signal named CLOCK. Then I prepared short simple module : module main_core(XCLK,LED); input XCLK; output LED; assign LED=XCLK; ...

Hi, I a newbie and also to DSP... Heres my question.. I have successfull implemented a custom bandpass filter design that will process a rpm...

Hi, I a newbie and also to DSP... Heres my question.. I have successfull implemented a custom bandpass filter design that will process a rpm signal (cranking 150rpm 100mVpp ~ high rev 2600rpm 2.2Vpp) to have a constant gain at the rpm range mentioned. The problem I seeing now is the phase difference of input to output of the filter around 30 to 60 degrees... Everything is perfect except for th...

Hi, can anybody kindly suggest me from where i can get FM receiver (demodulator) models to implement on SFF SDR Development platform....please...

Hi, can anybody kindly suggest me from where i can get FM receiver (demodulator) models to implement on SFF SDR Development platform....please help