Started by Keith E. Larson October 28, 2003
Hello Martin

Probably the first and formost thing to mention is that the bootloader is a
program running on the DSP.

When the VC33 starts in bootloader mode the bootloader code (in the internal
ROM) polls the INTx lines to see which ones are active in this order. INT3
(serial) INT0, INT1 and then INT2.

The first value that is read tells the bootloader the chunk size, followed
by some initialization and header information. The bootloader then reads
data into the DSP in what I like to call 'chunks' of 8, 16 or 32b width.
These in turn are concatenated into 32 bit values that will become the
instructions and data.

Boot information at 0x400000 is where the external VC33 DSK ROM is, so it
had better work!

More Bootloader Notes
The first read simply tells the bootloader the width and is only 1 byte. If
you are feeding the boot information via a FIFO, the DSK interface, or your
logic you need to know this!

The bootloader is a program running from the internal ROM. It makes calls
to functions and therefor needs to have a small stack space of 1 word. That
word is located at 0x809801 --> IN OTHER WORDS DO NOT TRY TO BOOTLOAD OVER

Extra L/A Hardware
As long as the loading is light (and it should be) no buffering should not
be a problem.

Anytime you hang something on a signal you have the potential of creating
signal integrity problems. Sometimes this is a care, sometimes not.

Consider for example the address or data lines. Poor signal quality will
affect the setup and hold times, but these are qualified by the PAGEx, STRB
and R/W control signals. As long as these signals are clean and stable on
the clock edges you can get away with really crappy signals. In other
words, simply slowing down the clock will fix these kinds of problems.
Peripherals like the serial ports and timers also fall into this catagory.

Now consider what happens if you corrupt a control signal! Here noise and
other junk can cause bogus reads, writes or bus conflicts and really mess
things up.

When the RPTS instruction is fetched (and has not been decoded yet) it will
be followed by one more instruction fetch that will ultimately be repeated.
Since the next instruction is now within a register the CPU can re-issue
that instruction N times without having to go back and re-read the
instruction from memory. This frees up the bus, but the CPU also happens to
be 'locked in' and executing this one instruction. The CPU therefor is not
servicing interrupts. If you need interrupts, use the RPTB instruction as
it is valid to have a block length of 1. The penalty of using RPTB is that
the opcode is constantly fetched potentially leading to bus conflicts and

Here are some more interesting ways to repeat chunks of code
; Adds 2*2*1 to R0
; the call pushes the next address creating a loop
Func call Next ; syntactically== $+1
Next call $+1 ;... this address+1
addi 1,R0 ;
rets ;
; the RPTB registers, RS, RE and RC can be preloaded
; well outside the innermost loop. An example would
; be an FFT where the innermost butterfly needs to
; start quickly
ldi @Addr_Loop1,RS ; Preload start
ldi @Addr_Loop2,RE ; Preload end
ldi 7,RC ; repeat 8x
:: ;
or RM,ST ; fast start repeat mode
Loop1 addi 1,R0 ; starts innermost loop
addi 1,R1 ; with only 1 cycle lost
Loop2 addi 1,R2 ;
rets ;
Addr_Loop1 .word Loop1
Addr_Loop2 .word Loop2
Hope this helps
Best regards,
Keith Larson

At 01:55 PM 10/28/03 -0000, you wrote:
Hello I'm Martin Argoit from Argentina, I'm work with a board that include
the DSP TMS320vc33-150, all bypass capacitors, the 2 supply plane (1.8 &
3.3V) and the ground plane. The doubts I have its because I'm new in this
and I don't want do something wrong . I'm using an logic analyzer with a
pattern generator to load the program.

For example:

-It's ok that I place the program I want to try in the memory 400000, when
I'm in the boot load mode?

-Must I use some hardware between the analyzer & the vc33, which one?

-How das it work the repeats (RPTS) function?

I hope that someone could help me.

Martin Argoit
|Keith Larson |
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