c5402 HPI timing question

Started by Jane Shen December 1, 2001

Hi, all,

Got a c5402 HPI timing question:

I am trying to interface to HPI at 100MHz bit/s data rate(12.5MHz
byte/s). I am acting as a host ONLY SENDING data to HPI. The control
signals used are HBIL/HRDY/HDS1/R_W/HCNTL0_1. From the c5402 spec(page
63, SPRS079E) I could not figure out the timing between the HDS and
HRDY. When sending the first byte, the HDS could only go high after the
HRDY goes high or HDS could always go high even though the HRDY is still
low? The bottom line is: is there any timing constraint here between the
HDS and HRDY(in case of only write to the HPI)? The spec doesn't say a
thing, but TI's other doc says that you have to wait the HRDY goes high.
I don't know if TI implement a FIFO or a double buffer between the HPI
data reg and the internal memory.

This is critical to me cuz we also have 6 DMA channels running all the
time after power on. This HRDY will be kept low for a significant time
period(106ns) while all the DMA channels are running. Is there anybody
here having the experience of interfacing HPI at high speed? Any
suggestion or comment will be very much appreciated. Thank you all in
advance. Best wishes