Started by February 23, 2018
I have two 1MHz ADCs and would like to interleave them
by a half of the sampling cycle in order to get a single
ADC with effective sampling frequency of 2MHz (I want to
oversample the signal by as much as possible). But the
aliasing properties of the data stream will be as if the
signal was sampled at 1MHz because the ADCs are independent
blocks and don't influence each other, right?

Best regards, Piotr
On 2/23/2018 3:41 AM, Piotr Wyderski wrote:
> I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz (I want to > oversample the signal by as much as possible). But the > aliasing properties of the data stream will be as if the > signal was sampled at 1MHz because the ADCs are independent > blocks and don't influence each other, right? > > &nbsp;&nbsp;&nbsp;&nbsp;Best regards, Piotr
You would need to trigger the two ADCs on the halves of the sampling cycle. I think you implied that. Because the ADCs are triggered with a fixed phase it's not correct to say they are independent blocks. Depending on the circuit details, you may need sample and hold circuits on each ADC input. Try a thought experiment. Use your ADC system to read a 1 MHz square wave that is in phase with your sampling signal. ADC #1 always sees 1V, and ADC #2 always sees 0V. -- Best wishes, --Phil pomartel At Comcast(ignore_this) dot net
Le vendredi 23 f=C3=A9vrier 2018 03:41:07 UTC-5, Piotr Wyderski a =C3=A9cri=
t=C2=A0:
> I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz (I want to > oversample the signal by as much as possible). But the > aliasing properties of the data stream will be as if the > signal was sampled at 1MHz because the ADCs are independent > blocks and don't influence each other, right? >=20 > Best regards, Piotr
benjamin.couillard@gmail.com wrote:

Thanks Benjamin and Phil, very informative! The issue turns out to be much more complex than I thought, but the graphs are also very promising -- the spurious spikes are exactly in the places where the signal isn't. Best regards, Piotr
On 23.02.18 09.41, Piotr Wyderski wrote:
> I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz (I want to > oversample the signal by as much as possible). But the > aliasing properties of the data stream will be as if the > signal was sampled at 1MHz because the ADCs are independent > blocks and don't influence each other, right?
If your ADC act as sample-and-hold then you have all properties of a 2 MHz ADC - assuming that they really sample alternatingly at 2MHz, of course. If your ADC have some analog bandwidth limitations, e.g. by averaging, then this bandwidth will be unchanged by the second ADC. Marcel
Marcel Mueller  <news.5.maazl@spamgourmet.org> wrote:

>If your ADC act as sample-and-hold then you have all properties of a 2 >MHz ADC - assuming that they really sample alternatingly at 2MHz, of course.
Yes, you really do want to simulate the effect of the possible sample time offset. I seem to recall there are weird artifacts, the effect of which is dependent on application. S.
On 2/23/2018 5:14 PM, Marcel Mueller wrote:
> On 23.02.18 09.41, Piotr Wyderski wrote: >> I have two 1MHz ADCs and would like to interleave them >> by a half of the sampling cycle in order to get a single >> ADC with effective sampling frequency of 2MHz (I want to >> oversample the signal by as much as possible). But the >> aliasing properties of the data stream will be as if the >> signal was sampled at 1MHz because the ADCs are independent >> blocks and don't influence each other, right? > > If your ADC act as sample-and-hold then you have all properties of a 2 > MHz ADC - assuming that they really sample alternatingly at 2MHz, of > course. > > If your ADC have some analog bandwidth limitations, e.g. by averaging, > then this bandwidth will be unchanged by the second ADC. > > > Marcel
If there's a S&H before the ADC (whether part of the ADC or a separate circuit), you can treat the ADC as a black box independent of how it works inside. The analog bandwidth was stated to be 1 MHz. -- Best wishes, --Phil pomartel At Comcast(ignore_this) dot net
On 2/23/2018 1:50 PM, benjamin.couillard@gmail.com wrote:
> Le vendredi 23 f&eacute;vrier 2018 03:41:07 UTC-5, Piotr Wyderski a &eacute;crit&nbsp;: >> I have two 1MHz ADCs and would like to interleave them >> by a half of the sampling cycle in order to get a single >> ADC with effective sampling frequency of 2MHz (I want to >> oversample the signal by as much as possible). But the >> aliasing properties of the data stream will be as if the >> signal was sampled at 1MHz because the ADCs are independent >> blocks and don't influence each other, right? >> >> Best regards, Piotr > > > > Check out this article from Analog Devices > > http://www.analog.com/en/analog-dialogue/articles/interleaving-adcs.html >
Excellent article. Thanks. -- Best wishes, --Phil pomartel At Comcast(ignore_this) dot net
Piotr Wyderski <peter.pan@neverland.mil> writes:

> I have two 1MHz ADCs and would like to interleave them > by a half of the sampling cycle in order to get a single > ADC with effective sampling frequency of 2MHz (I want to > oversample the signal by as much as possible). But the > aliasing properties of the data stream will be as if the > signal was sampled at 1MHz because the ADCs are independent > blocks and don't influence each other, right? > > Best regards, Piotr