On 03-06-2008 at 13:53:15 faz <fazulu.vlsi@gmail.com> wrote:> Step by step. How would you verify an apple? > I am already confused and i dont know wat your r trying to explain > here..And I'm confused about your "how to verify FIR" question. How to verify FIR is exactly the same as to verify an apple. It will be extremely long way. Start with usenet netiquette. http://www.cs.tut.fi/~jkorpela/usenet/dont.html -- Mikolaj

# Testing FIR filter design

Started by ●June 2, 2008

Reply by ●June 3, 20082008-06-03

Reply by ●June 3, 20082008-06-03

Mikolaj wrote:> On 03-06-2008 at 13:53:15 faz <fazulu.vlsi@gmail.com> wrote: > >> Step by step. How would you verify an apple? >> I am already confused and i dont know wat your r trying to explain >> here.. > > And I'm confused about your "how to verify FIR" question. > How to verify FIR is exactly the same as to verify an apple. > > It will be extremely long way. > Start with usenet netiquette. > http://www.cs.tut.fi/~jkorpela/usenet/dont.htmlIt's a language problem. give him a break. Faz: You need to specify what you mean by "verify". "Verify" could mean any one of several things, or a combination of them. 1. Is it really an FIR filter? 2. Does the filter behave according to the design? (is the code good)? 3. Is the filter's impulse response correct (is the design good)? 4. Will the worst-case signal cause the filter to saturate? I assume that you mean "verify proper performance". Start with two tests: 1. Feed the filter with all zero samples. The output should be all zero. 2. Change one of those zeros to a one, The output should be the filter's coefficients. Then check for overflow. 3. Feed the filter with all maximum values, setting the sign sequence to the same as the filter coefficients. One output samples will be the sum of the coefficient's absolute values, times the maximum input value. If that doesn't overflow, you're set. Jerry -- Engineering is the art of making what you want from things you can get. ???????????????????????????????????????????????????????????????????????

Reply by ●June 3, 20082008-06-03

1. Is it really an FIR filter? Yes it is a FIR filter 2. Does the filter behave according to the design? (is the code good)? 3. Is the filter's impulse response correct (is the design good)? I have done impulse test all the coefficients are coming out properly 4. Will the worst-case signal cause the filter to saturate? I dont know wat this means Feed the filter with all maximum values, setting the sign sequence to the same as the filter coefficients I will do this test..by the way feeding with maximum value should be same as maximum value in filter coefficients?? Thanks for your suggestions.... regards, faz Jerry Avins wrote:> Mikolaj wrote: > > On 03-06-2008 at 13:53:15 faz <fazulu.vlsi@gmail.com> wrote: > > > >> Step by step. How would you verify an apple? > >> I am already confused and i dont know wat your r trying to explain > >> here.. > > > > And I'm confused about your "how to verify FIR" question. > > How to verify FIR is exactly the same as to verify an apple. > > > > It will be extremely long way. > > Start with usenet netiquette. > > http://www.cs.tut.fi/~jkorpela/usenet/dont.html > > It's a language problem. give him a break. > > Faz: You need to specify what you mean by "verify". "Verify" could mean > any one of several things, or a combination of them. > 1. Is it really an FIR filter? > 2. Does the filter behave according to the design? (is the code good)? > 3. Is the filter's impulse response correct (is the design good)? > 4. Will the worst-case signal cause the filter to saturate? > > I assume that you mean "verify proper performance". > > Start with two tests: > 1. Feed the filter with all zero samples. The output should be all zero. > 2. Change one of those zeros to a one, The output should be the filter's > coefficients. > > Then check for overflow. > 3. Feed the filter with all maximum values, setting the sign sequence to > the same as the filter coefficients. One output samples will be the > sum of the coefficient's absolute values, times the maximum input > value. If that doesn't overflow, you're set. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ???????????????????????????????????????????????????????????????????????

Reply by ●June 3, 20082008-06-03

faz wrote:> 1. Is it really an FIR filter? > Yes it is a FIR filterI didn't mean to ask. It was a suggestion for what to do.> 2. Does the filter behave according to the design? (is the code > good)? > 3. Is the filter's impulse response correct (is the design good)? > I have done impulse test all the coefficients are coming out properlyThat's most of it. Have you verified that the impulse response has the correct response?> 4. Will the worst-case signal cause the filter to saturate? > I dont know wat this meansIt means:> Feed the filter with all maximum values, setting the sign sequence to > the same as the filter coefficients > > I will do this test..by the way feeding with maximum value should be > same as maximum value in filter coefficients??It should be the largest sample you will apply. Usually, full scale.> Thanks for your suggestions....You're welcome. Jerry -- Engineering is the art of making what you want from things you can get.

Reply by ●June 3, 20082008-06-03

On 03-06-2008 at 15:56:58 Jerry Avins <jya@ieee.org> wrote:> It's a language problem. give him a break.(...) I don't think so. It's a general understanding problem. I was trying to show him a way but it is useless. He is just asking and not answering. He's acting entirely blindly. -- Mikolaj

Reply by ●June 3, 20082008-06-03

On Jun 3, 12:07�pm, Jerry Avins <j...@ieee.org> wrote:> faz wrote: > > 1. Is it really an FIR filter? > > Yes it is a FIR filter > > I didn't mean to ask. It was a suggestion for what to do. > > > �2. Does the filter behave according to the design? (is the code > > good)? > > �3. Is the filter's impulse response correct (is the design good)? > > I have done impulse test all the coefficients are coming out properly > > That's most of it. Have you verified that the impulse response has the > correct response? > > > �4. Will the worst-case signal cause the filter to saturate? > > I dont know wat this means > > It means: > > > Feed the filter with all maximum values, setting the sign sequence to > > � � �the same as the filter coefficientsJerry, Shouldn't these data signs be in reverse order of the coefficient signs if they are being fed in? Dirk> > > I will do this test..by the way feeding with maximum value should be > > same as maximum value in filter coefficients?? > > It should be the largest sample you will apply. Usually, full scale. > > > Thanks for your suggestions.... > > You're welcome. > > Jerry > -- > Engineering is the art of making what you want from things you can get.

Reply by ●June 3, 20082008-06-03

dbell wrote:> On Jun 3, 12:07 pm, Jerry Avins <j...@ieee.org> wrote:...>> It means: >> >>> Feed the filter with all maximum values, setting the sign sequence to >>> the same as the filter coefficients > > Jerry, > > Shouldn't these data signs be in reverse order of the coefficient > signs if they are being fed in? > > DirkYes. To keep the explanation as simple as I believe the problem is, I assumed a symmetrical filter and a lack of interest in the sign of the result. Thank you for making the condition explicit. ... Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������

Reply by ●June 3, 20082008-06-03

Mikolaj wrote:> On 03-06-2008 at 15:56:58 Jerry Avins <jya@ieee.org> wrote: > > >> It's a language problem. give him a break. > (...) > > I don't think so. It's a general understanding problem. > I was trying to show him a way but it is useless. > He is just asking and not answering. > He's acting entirely blindly.So let's give him the tools to prove you right. Jerry -- Engineering is the art of making what you want from things you can get. ???????????????????????????????????????????????????????????????????????

Reply by ●June 3, 20082008-06-03

On 03-06-2008 at 20:51:33 Jerry Avins <jya@ieee.org> wrote:> Mikolaj wrote: >> On 03-06-2008 at 15:56:58 Jerry Avins <jya@ieee.org> wrote: >> >>> It's a language problem. give him a break. >> (...) >> I don't think so. It's a general understanding problem. >> I was trying to show him a way but it is useless. >> He is just asking and not answering. >> He's acting entirely blindly. > > So let's give him the tools to prove you right. > > JerryBut he is not willing to co-operate. I think he don't want to understand, don't want to learn, don't want to read and don't want to talk. He didn't read the netiquette, this is one example. He is trying to verify an apple an does not see anything strange with that. -- Mikolaj

Reply by ●June 4, 20082008-06-04

But he is not willing to co-operate. Without learning resources i am not blindly designing a FIR filter...do u think it is possible...Might be my understanding is not to the maximum level as u r excepting as i am new to dsp..I have been updating till i reach that level...can u share some links,good resources about the FIR filter design and verification... Let me clear u first wat i have done so far...Before designing i red all the FAQ of this groups about FIR filter design and followed by other resources in the net.Even i refered books like discrete time signal processing,digital filter designers handbook and practical analog and digital filter design(if u knew some more books send the link of the same).Then decided to design a FIR filter to that can support upto 256 taps and generated the coefficients using equiripple design method with direct form 1 structure using the FDA tool of MATLAB. I have done systemverilog coding for implementing the design in FPGA...for that i will take coefficients and input samples generated from MATLAB as inputs to the filter and compute the response... To verify it i have done impulse test and checked in the simulation all the coefficients are coming out...As suggested by jerry i will be doing overflow test before implementing the design in FPGA...And i asked this group to knew if there r other test cases to make my design more perfect... I think i explained from my side...Is it clear to u...give your comments and suggestions On Jun 4, 2:00�am, Mikolaj <sterowanie_komputer...@hahapoczta.onet.pl> wrote:> On 03-06-2008 at 20:51:33 Jerry Avins <j...@ieee.org> wrote: > > > Mikolaj wrote: > >> On 03-06-2008 at 15:56:58 Jerry Avins <j...@ieee.org> wrote: > > >>> It's a language problem. give him a break. > >> (...) > >> �I don't think so. It's a general understanding problem. > >> I was trying to show him a way but it is useless. > >> He is just asking and not answering. > >> He's acting entirely blindly. > > > So let's give him the tools to prove you right. > > > Jerry > > But he is not willing to co-operate. > I think he don't want to understand, > don't want to learn, don't want to read > and don't want to talk. > He didn't read the netiquette, this is one example. > He is trying to verify an apple > an does not see anything strange with that. > > -- > Mikolaj