The IRQA and IRQB can be individually controlled using the IBL and IAL
bit fields in the IPR. Using these bits the IRQA and IRQB can be
individually masked. The IPR also allows for masking and unmasking of the
different priority level interrupts by manipulating the CH0 through
CH6 bits.
The discussions on this subject between the Family manual and the user
manual are confusing. The family manual explains how the 56800 core operates.
The 56F80x user manual details the 56F80x peripherals. The ITCN is a
chip peripheral and not part of the 56800 core. The 56800 core has several
interrupt sources that it recognizes. These are the Hardware
Reset, COP Watchdog Reset, Illegal
Instruction Trap, SWI, Hardware Stack
Overflow, IRQA, RQB, and the chanel 0
through 6 interrupts. The 56800 core is fully responsible for recognizing and
altering the program flow of the core to service these interupt
sources.
The ITCN controls and manages the peripheral interrupt signals and
requests interrupt services from the 56800 core. It requests the interrupt
services by using the core CH0-CH6 interrupt signals. These are
the signals that are controlled in the IPR. At any given clock cycle
the ITCN scans the input interrupt signals from the peripherals and determines
if a specifc peripheral is requesting an interrupt and what is the highest
priority interrupt request is and it in turn uses the appropriate CHX
signal to request an interrupt from the 56800 core. The ITCN will also
provide an ISR vector to the core.
The IPR and SR are core registers. The SR bits I0 and I1 bits control
whether the core maskable interrupt sources are masked or unmasked. The
peripheral interrupt sources are also globally masked and unmasked since the
ITCN uses the CH0-CH6 core interrupt signals to request interrupt services from
the core. The Family manual in chapter 7 describes how the core handles
interrupts. This material is not in the user manual because the user manual only
has material on the chip peripherals and the chip integration.
Hope this helps on giving some back ground on what is going on.
Thanks.
[Hutchings William-p23437] -----Original
Message-----
From: m...@bish.net [mailto:m...@bish.net]
Sent: Thursday, August 07, 2003 8:52 AM
To: Corey, Rick
Cc: 'Johnson, Jerry'; m...@yahoogroups.com
Subject: RE: [motoroladsp] Interrupts (masking them all) - 56805
On Thu, 7 Aug 2003, Corey, Rick wrote:
> Hi
Jerry
>
> I think the external IRQs IRQA and IRQB are maskable
by setting SR:I-bits
> (page 4-4, section 4.2 of my 5680x User's
Manual, Rev.2).
Yes, that's how I am masking them - but when you
do that you mask all
level 0 interrupts (which include all on-chip
peripherals, timers, serial
ports, etc)
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