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time recovery algorithm and CORDIC

Started by Ali23 1 month ago13 replieslatest reply 3 weeks ago143 views

I need your help in understanding how to simulate a timing recovery algorithm. I have already read a lot of literature � but I have still doubts how it works.

Let me briefly explain MY SIMULATION:

  • Create a test signal:
  • BPSK, 1000 symbol with 16 samples
  • Raised cosine filter
  • Compute an amplitude and phase of each sample (CORDIC)
  • Create N ( = 1000 / (32*16)) blocks: 32 x 16
  • Selects sample from the time-index one greater than that of the on-time sample is the late sample, and the sample from the time-index one less than that of the on-time sample is the early sample.
  • Compute an error (= late sample - early sample)
  • Depends on the error I shift one sample before or after

MY QUESTIONS ARE:

  • And after that I don’t know what my next step is?
  • What should I do with the computed error?
  • If I know the sample with max amplitude, do I need the time recovery algorithm at the receiver side?
  • How can I compensate the phase offset in this way?
  • Guys, does anyone have an example of simulation in Matlab or in C?
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Reply by weetabixharryMarch 5, 2021

The rough idea is that the +/- sign of the error should tell you to either increase or decrease the sample rate in your receiver.

The point is that the sample clock in your receiver is not identical to the clock in the transmitter. So the rates of the two clocks will be slightly different (and, over time, their rates will also drift relative to each other).

So the receiver needs to try to figure out where the BPSK symbol points are in time, then carefully adjust its sample rate so it samples at precisely the right times (bang on the BPSK symbols). This "early-late" method is a simple and efficient way of achieving this.

If you are simulating the whole system, then bear in mind that you need to simulate the timing imperfections, otherwise no timing recovery will be required. (For example, you could resample the BPSK signal by a ratio of 0.9999 or 1.0001 - but make sure you don't use a resampling filter that will mess up your nice raised cosine response).

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Reply by kazMarch 5, 2021

If your focus is on simulation then the first step is to have your symbols vector as if sampled by ADC. This is the essence of your work. If you don't get this right all else is not useful.

To model ADC upsample your test signal then downsample it back changing the symbol peaks i.e. apply decimate with fractional delay on the upsampled test vector.

Once you grab that then you need to dynamically change the fractional delay (at random).

The second issue once your algorithm of time detection works is to apply error as feedback to an ADC (if applicable) or to a resampler based fully digital timing recovery. This is not domain of beginners I am afraid but we all learn through practice.

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Reply by neiroberMarch 5, 2021

Hi Ali,

A good introductory reference for timing recovery is in Michael Rice's book:  "Digital Communications, A Discrete-Time Approach". Pearson Prentice Hall, 2009.  See Chapter 8.  Clock recovery typically involves a PLL -- see appendix C of Rice's book.  You can also take a look at my post about PLL's here.  I agree with Kaz that this is not a simple problem -- besides making the timing error detector function work, you typically have to embed it in a timing-recovery loop (except for burst demodulators).

regards,

Neil

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Reply by fharrisMarch 5, 2021

hi neil, have a look at attachments


sdr_part_22.pdf 

Lets_assume_System_synchronized_2.pdf

modem_2012_timing_demo_1.m



good to see you (your picture at least)

regards to family


fred

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Reply by neiroberMarch 5, 2021

Hi Fred,

Thanks.  I really like "Lets assume the system is Synchronized".  I would change your (non-jive) sampler to read:

"If Mama ain't happy, ain't nobody happy".

Neil


[ - ]
Reply by fharrisMarch 5, 2021

Hello Ali

You have to program the front end of an IQ receiver. It has to have a pair of sqrt Nyquist matched filters running at 2-samples per symbol (same as shaping filters in your modulator), also need a derivative matched filter to help locate peak of correlator (matched filter output), a product detector y times y_dot, and a timing recovery PLL. You have two choices... the first is a polyphase interpolator that will shift the sample locations from where they are to where they need to be to be aligned with correlator peak.

The second is a polyphase bank of matched filters, each aligned with small time offsets between sample clock locations and peak amplitude locations. The timing recovery loop can interpolate to the correct time offset or can shift between possible matched filters till it identifies the best fit for the timing offset. The paper and the matlab script shows how this happens. 

I tried to upload a tutorial i have on synchronization. too big! if you send me your email address I'll send it to you. Also Bernie Sklar and I have just released the 3-rd edition of his digital communications book. We have a chapter in it on synchronization (Chapter 10). Similarly, my book on multirate signal processing has a section on synchronization... new edition out in 10 days!   

my email.... fjharris@ucsd.edu


modem_2012_timing_demo_1.m

Lets_assume_System_synchronized_2.pdf

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Reply by Ali23March 18, 2021

thank you

ani.kom1920@gmail.com

[ - ]
Reply by Aida92March 30, 2021

Hello fharris!

Could you share with me too?

sasdam12@yandex.ru


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Reply by Mannai_MuraliMarch 6, 2021

Please read Meyr 'Digital Communication Receivers Vol2' and Phase lock techniques By Gardner.I have a reference code for QPSK Receiver, NDA Timing Recovery.

If you contact me I can help you and you modify the code.

Mannai_Murali@hotmail.com

Skype: Mannai_Murali

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Reply by weetabixharryMarch 6, 2021

@Mannai_Murali Why not share your code here in the forum so someone else may benefit from it in the future?

@Ali23 Do you specifically need an example in MATLAB or C? I could quite easily put together a C++ example, but I don't have all the building blocks written in MATLAB or C.

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Reply by fharrisMarch 7, 2021

Hello, all, this is a timing recovery loop using a polyphase matched filter and derivative matched filter works like a charm.


fred h

modem_timing_32.m
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Reply by Mannai_MuraliMarch 26, 2021

The QPSK Receiver code with NDA Timing Recovery is attached.I wrote it long back.If some one needs help I have to go through for a day.It uses NDA Timing Algorithm.

I tested only tracking.If I start at middle of a symbol it was not working.But if I start at correct timing phase it tracked the timing inaccuracy of receiver crystal at 100 ppm.i tested it by opening the tracking loop then BER build to 0.5.Closing the loop BER wa small.At that time I did not know how to select Loop Filter (Proportional plus integral) coefficients.Now I know.If some one wants to learn I can help after a week from know.The theory behind NDA was taken from Digital Communication Receivers from Meyr.

By proper selection of loop filter I hope acqisition alo Muraliwill work.

For better learning of Digital Phase Locked loop one may refer Floyid Gardner.

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Reply by Aida92March 30, 2021

Hi

whre can i find info about NDA Timing Algorithm?