Interpolate complement value

Started by fpgaplayer 7 years ago4 replieslatest reply 7 years ago143 views

I read a doc http://www.analog.com/media/en/technical-documenta... , page 49 AD9119_9129_page49.pdf , found an interesting implementation. I greatly appreciate If somebody here who have time to give more details about this interpolation.

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Reply by drmikeDecember 20, 2016

Look at page 45 Figure 137.  That is the 2x interpolation filter.  I think it means you can update the DAC twice as fast as the input clock by changing the data on both rising and falling edges.  I'm not sure what you lose by doing that, but there must be both advantage (you go twice as fast) and disadvantage for each choice of signal routing.  Pretty cool part in any event, 5.7 GHz sample rate is pretty quick.

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Reply by Tim WescottDecember 20, 2016

They say (on p. 45) that the filter is being clocked at 2x the data input rate, and is interpolating the data.

So, it's basically putting a reconstruction filter inside the DAC, to ease the design of the external analog reconstruction filter.

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Reply by Tim WescottDecember 20, 2016

I'm not sure that anyone outside of ADI has the real nitty-gritty details, but from reading the pertinent parts of the data sheet I gather that they're doubling the clock and then running a FIR filter and the DAC at that doubled clock rate, and using the result to shape the output response.  As they said, this would ease the requirements on the external reconstruction filter.

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Reply by fpgaplayerDecember 20, 2016

Thank you very much @drmike and @Tim Wescott, I am sorry I didn't say clearly, I mainly care about the Mix-Mode in the doc.


In short, what are the differences for interpolate zeros, interpolate same data last sample, and interpolate the complement value of the last sample? Especially the differences in engineering project.