Hello,
I would like to understand the process of 'near IQ' sampling. I might be using incorrect terminology (so please correct me if this is true) but the idea of near IQ sampling is that you can sample a high frequency signal with a much lower sample rate as long as the sample frequency is much higher than the variations in the high frequency signal.
Is this process called 'near IQ sampling'?
I am having trouble finding papers or tutorials on this topic. I might have the wrong term, but I would greatly appreciate it if you could help point me towards useful search terms so that I can educate myself on this topic.
All I can find on the topic:
https://accelconf.web.cern.ch/l06/papers/thp004.pd...
http://recycle.lbl.gov/~ldoolitt/llrf/neariq.pdf
Best Regards,
James
Dear James, what you are referring to is 'aliasing' or 'down-sampling', it is very much like digital mixing. In very general terms, the 'variation' you mention is called modulation, and the prerequisite is that the sampling frequency has to be at least twice the maximum frequency component of this modulation (look up Nyquist), otherwise the modulation component will be aliased (frequency components higher than half the sampling frequency will appear incorrectly as lower frequency components). When you down-sample the high frequency 'carrier' signal it will appear as a much lower frequency signal, but with the same modulation. This technique is common practice in the final stage of GPS receivers. Often it may be necessary to apply a bandpass or lowpass filter to the signal before sampling to ensure no modulation aliasing occurs. Hope this helps.
I will call it sub-sampling i.e. your sample rate is twice bandwidth of signal and not twice max frequency as dictated by Nyquist rule. You get the alias and use it instead...
Some may call it down sampling but I prefer sub-sampling.
The term I have heard in the past is "quadrature sampling".
ADC data sheets provide additional clues based on the ADC's input bandwidth. Some of that is based on how fast the ADC can convert. When sampling a signal that's faster than the ADC sample rate, then something else must be done to mitigate Nyquist issues, namely use an ADC that has a built-in high-speed sample and hold (S/H) or employ an external S/H. But this brings issues of it's own into the picture, like "droop rate" (sample amplitude decay with time) related to the S/H bandwidth, and sample capture time. This allows one to capture a signal that is "faster" than the ADC's conversion rate, but only if you do the other mitigation mentioned by everyone else here that ensures that the sub-sampled signal does not alias on top of some other signal artefact that interferes with the desired signal.
It looks like nobody looked at your references. In a generic sense I think there are a couple of different concept getting conflated, and to be honest I'm not sure how they apply to the klystron application that you appear to be looking at.
In general, though, there are two different concepts:
1. IF sampling, as it is known in the communications world, where a bandpass signal is sampled at greater than its bandwidth, but at a rate much less than the actual frequency content of the signal. Your first link touches on this a bit. This often has nothing to do with IQ or quadrature sampling, like in the context of the application cited in the link. This is a way of saving samples by sampling at a lower rate than might otherwise be necessary, but it requires an ADC and sample amplifier with very good jitter characteristics.
2. Quadrature sampling. This is a separate concept from IF sampling, and involves taking two samples at a time in quadrature. This results in an IQ pair for each sample. Your second link shows shifting the quadrature phase relationship slightly so that the samples aren't really orthogonal any more, presumably to help with some ADC impairments, but I'm not quite sure what the actual issue is or what problem they're trying to solve by doing that. Historically many practical systems didn't quite sample exactly in quadrature, anyway, so corrections or adjustments were made to correct it. It's not a totally unusual thing, but I don't think I've seen it done intentionally before.
I hope that helps a little bit.
This reference seems to explain the application requirements quite well, and clearly makes the distinction between sub-sampling and the "non-IQ" concept
This is also referred to as “undersampling”. Key requirements and considerations to do this properly are that the analog input bandwidth of the ADC surpasses the signal frequency (regardless of sampling rate), and a bandpass filter is implemented prior to sampling to avoid degradation due to aliasing. Also undersampling increases sensitivity to clock jitter so may require a higher quality sampling clock
