I am new in #FPGA programming, yet I have programming experience in using C, matlab, SQL, and other languages.
I am assigned a task of creating a Windowing function using Xilinx FPGAs in VHDL. I studied what windowing is and how it works. I have also done couple of examples in BRAMs, Dual Port RAMS, etc, and I did windowing function tutorials available in Vivado applications as examples. I am failing to put the whole thing together (like reading data from BRAM and multiplying it with signals coefficients). May I please be given the direction/logic on how do I approach this.
Any advice will be appreciated
I guess you want to apply a window to an array of samples stored in Bloc RAM.
My experience with Spartan 3 (it doesn't change the matter as BR are similar or bigger now). Multiplication of an the array of samples (Signed samples) with a constant positive window array (Signed samples normalised).
A simple counter can be used to address both the sample array and the constant window array. And you need to store the sample at the output of the FPGA (Back in the BR).
I hope it help,
Do you perhaps know of any source where I can get temporal samples, just for testing
Thanks in advance
It's just an element-by-element multiplication, so a structure with a counter or two and a multiplier is basically it. If the window function is symmetric, which most are, and memory is constrained, you can cut the memory in half and add a little logic to reverse the counter when you get to the middle.
If resources are REALLY constrained you may end up needing to find windowing functions that are a better fit with the resources and finding which is most acceptable, rather than starting with the theoretically bestest and finding how to implement it.
This day and age, though, unless you're in a really high-volume price constrained market, or building a device that's power, or space, or otherwise constrained, you'll probably just throw more memory at it.
Never discount the benefits of googling something, which too often is greatly affected greatly by how a search is phrased. I used "dsp window function for fpga" and got lots of hits.
It seems that although you have programming experience, you may not have FPGA experience (I don't either BTW) and may lack DSP experience too. I always start by examples of other (via the search above) and then build on that. I would work first in familiar turf by programming in MatLab or C and then build from there. In spite of VHDL being Cish, it has lots of nuance that comes with lots of reading, examples, and study.
If you are more comfortable with C or MATLAB and you dont't have to become an FPGA expert in the near future, you should look at HDL code generation solution from C or MATLAB.
I couldn't say a better advice!
Try Vivado HLS from Xilinx, you'll get what you need in a few minutes.