Loop bandwidth for symbol timing recovery

Started by avi1987 3 years ago4 replieslatest reply 3 years ago211 views


I am trying to design the Symbol timing recovery(#STR) block of #DVBS Receiver. 

How should I chose the loop bandwidth and damping ratio for determining the loop filter coefficients k1 and k2.

In some literature they are given as BnTs= 0.005, zeta = 1/sqrt(2),

while in others it is given as BnTs= 0.05, zeta = 1. 

How should I proceed for choosing the Bn and zeta?

Should BnTs factor change as we change Ts (say from 0.1 to 0.00001 sec)?

Regards avi

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Reply by Tim WescottMay 27, 2016

If Bn is the bandwidth in Hz, then for roughly the same loop performance it should probably remain approximately constant as you change Ts.

You should choose the bandwidth so that the receiver can lock adequately fast, and hold lock reasonably well in low SNR conditions.  I'm pretty sure that you don't need to worry about Doppler -- this is for geosynchronous satellites, yes?  If Doppler is an issue, then you need to hold lock reasonably well as the frequency shifts.

Locking quickly demands a high bandwidth.  Holding lock in low SNR conditions demands a low bandwidth.  Holding lock against rapid frequency shifts demands a high bandwidth, or a more complicated loop.

If you're serious about this, you might want to gain an understanding of how PLL loops actually work (not just how to draw a block diagram or write some code), so that you can do the engineering tradeoffs yourself.

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Reply by avi1987May 27, 2016

Thanks for your reply.

Could you kindly point to some useful literature regarding the locking of PLL particularly related to timing recovery. I have gone through some generalized PLL articles but unable to synchronize the material when Timing error detectors are used in place of phase detectors during symbol timing recovery.

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Reply by Tim WescottMay 27, 2016

You want a book, and you probably want a book recommended by someone other than me.  I say this because my go-to book on this subject is "Phase Locked Loop Circuit Design" by Dan Wolavar (Prentice-Hall, 1991).  He's one of those old-school analog circuit designers who treat digital solutions to these sorts of problems as if thinking about them might make his flesh rot and fall off his bones.  The book was extremely useful to me, but my original training was in analog circuits so it's quite easy for me to translate from resistors & caps & op-amps to lines of code.

Just about any introductory book on phase-locked techniques should* include at least one chapter on clock and data timing recovery. Moreover, a serious tome on the subject in the 21st century should at least reference alternate methods that are completely impractical for analog circuits but eminently feasible when you're doing the work digitally.  So if no one else steps in and recommends something, I'd suggest looking for well-received books written in the last twenty years that do mention digital techniques and that do mention carrier & timing recovery.  A quick search on Amazon, with dives into the tables of contents where appropriate, should get something worthwhile.

* "should include" is a moral judgement, not an indicator of what you can reasonably expect -- do check tables of contents if you are forced to buy a book blind.

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Reply by SlartibartfastMay 27, 2016

There are two texts that come up a lot for this:

Digital Communications Receivers, Synchronization, Channel Estimation, and Signal Processing, by Meyr and Moeneclaey, 


Synchronization Techniques for Digital Receivers, by Mengali.

Either should be a reasonable first reference.