Hello all, I am new to #SDR having done mostly hardware design
I have an external data stream incoming at 2kbps and being sampled by a GRC program at 48kSps via an audio card. That works fine.
However I wish to sample that sample stream once every 24 samples and at a particular point ("decision point") so that I can detect the bits, rather than samples. In hw I would use a D flipflop clocked from the bit clock with an adjustable delay across the bit.
If I simply resample or downsample, I cant control the sampling instant within the bit which I wish to do manually ie: I adjust a slider to select the instant to sample (see image)
Could someone suggest how to implement sampling at a particular instant in GRC..using existing blocks...as I'm not up to writing my own yet ?
The attached image shows the sampled bit clock, and the sampling instant identified(red and green strobes). What is not shown is the clock data stream I wish to sample.
Any hints would be much appreciated on how to sample this instant into a new bit stream, so I can then modulate it etc.
This is often done with a Timing Error Detector, a timing loop filter, and a resampling filter. If the existing samples are spaced closely enough that you don't need interpolation, you can still use the symbol timing recovery loop to select and track the closest sample and not bother with the resampling filter to do the interpolation.
This is a fairly esoteric topic that requires study and experience to get right, but it's the common solution to the problem. It is covered in many digital communications texts, usually under "symbol synchronization" or "timing recovery" or something like that.
Thanks for your suggestion. Ive tried using a Polyphase Clock Sync block...but cannot get it to sync to the incoming data. Normally with hw you would recreate a bit clock from incoming data..which is phase locked to the data..and then use that clock to sample the data into "bits". Maybe I need to play with the settings more ?
An inferior solution is that I create the bit clock in GR, output it to clock the sequence generator which I then sample. In this way the clock and data are synchronized.... but the down side is I have to create the bitclk....not an independent solution.
In both cases I still want to know how to select one sample from the 24 samples per symbol..which can be used to determine as to whether that BPSK symbol is a 0 or a 1. So I start with say, n x 28 samples per n symbols, and end up with n bits...which I then want to use as my data source for modulation etc.
Reading the bit stream is not the end of the exercise..its just the beginning.
THanks for any more hints which I can follow up.
A synchronization block will have a number of components, and they have to be appropriate for the signal and situation. If you can break out the Timing Error Detector, or somehow see its output, you should see a sawtooth that crosses zero at the timing instant. This assumes that it takes every sample as an input, but that's the function of the TED. I'd start there, but there's a lot that needs to be right. The sense of the loop could be backwards, too. There are a lot of things that might be wrong.
As I mentioned, synchronization is a fairly complex topic that requires some knowledge and experience or maybe luck to get going. Just putting a block down and hoping it works is often a frustrating exercise.
Thanks for your reply.Much appreciated.
Ive used a simpler approach to recover the bitclock from the data and it works well.
I thought Id show it in case its useful to others.