Any pointers to implementation of polyphase #CIC decimation filter implementation?
The traditional notion of "decimation filtering" is to lowpass filter a signal and then decimate the filter's output sequence. With polyphase decimation filtering, for computational efficiency reasons, the decimation is implemented before the filtering. That sounds
counterintuitive, but it is possible. The best I can do for you here is to point you to some online tutorial material.
For an introduction to traditional CIC filters, see:
For an introduction to the general idea of polyphase FIR filtering, see:
P. P. Vaidyanathan's scholarly (and lengthy) description of polyphase FIR filtering can be found at:
For polyphase implementations of CIC filters, see:
Thanks for the reply and the materials provided.Also, sorry for not being clear with my question.
I am yet to go through the links you have provided, but what I wanted to know was, has someone implemented of polyphase recursive CIC filter.
If you mean "has anyone in the world implemented..." then the answer is yes -- just about every sigma-delta ADC I've ever looked at includes a CIC filter.
If you mean "has anyone in this group implemented..." then to my knowledge the answer is yes, too -- I haven't, but I'm pretty sure that others here have. I've implemented integral comb filters for decimation, but not cascaded ones.
But this may not help you much -- the arithmetic and theory are pretty clear, and an accurate and complete block diagram is pretty simple. This means that your implementation is going to be mostly influenced by the environment you're putting it in, and far less by the "CIC-ness" of the thing.
So, figure on a few lines of code for the actual filtering, and five to ten times as much code that depends on where you're putting it.
Thanks for your reply. I have implemented CIC too in my system for the sigma-delta ADC. But is any implementation available for the same where data is coming out in parallel form (For eg, two 4-bit output at 750MHz instead of one 4-bit output at 1.5GHz). Can I do a parallel implementation for the CIC or do I merge the data back to single 4-bit at 1.5GHz?
Let's call the two channels \( x_1 \) and \( x_2 \). Are they two channels that must be kept independent, like from two antennas or the outputs of a quadrature converter? Or are they effectively samples of a 1.5GHz data stream that's being presented to you eight bits at a time at half the rate? Or is something even odder going on?
In the first case, of course, you need two independent filters.
In the second case, then (taking all due respect for pipeline delays and whatnot), just add them together and treat the resulting \( x_1 + x_2 \) term as a 5-bit input at 750MHz.
In the third case -- well, it's back to not enough information.