I was just explaining to my last remaining customer that when I need to do a phase locked loop in DSP, as likely as not I open my 28 year old book on phase locked loop circuit design, and translate from op-amps and caps and resistors to DSP algorithms, in my head.

Being a 100% software engineer, he can't do that, and since I'm working very part-time on this, he needs to feel confident taking as much of this out of my hands as possible.

I'm looking for a good description of doing continual bit timing recovery on NRZ data.  The technique I'm using currently is the bog-standard one of delaying the incoming samples by 1/2 a bit period, multiplying the original and the delayed versions together, and then multiplying that by a sine wave at the bit sample clock frequency to get a phase error, then finally running the thing through a PLL.  (The noise characteristics of the problem are such that doing data-directed synchronization is not the right approach).

I cannot for the life of me find a decent discussion of this technique on the web.  It seems like something that ought to be floating out there, but aside from some class notes, I'm repeatedly coming up with nothing.

So I'm looking for suggestions for

• Books that treat this problem in a way that someone with a pure software background can understand
• Articles, ditto
• Just freaking keywords that we can use to do searches (for God's sake!)

TIA.

This treats the theory, but no code examples.  :(

http://www.compdsp.com/presentations/Jacobsen/abin...

There is a huge literature base on this. Search for "digital PLL" or more specifically "digital PLL symbol rate recovery".

A good book is "Digital Clocks for Synchronization and Communications". However, all of these books have more of an engineering than computer science approach. That is what drove me to write a DSP text for non-engineers, but the section on PLLs in my book is rather short, although there is also a section on timing recovery, which explains the technique you mention.

Y(J)S

Hello Y(J)S. What's the title of your book?

DSPCSP (Digital Signal Processing, a Computer Science Perspective - Wiley 2000)

Hello Y(J)S. Ah ha. I've seen that book's cover on the Internet before. Congratulations on having your book published.

Actually, it was published 19 years ago and is already sold out (except for the India and China versions).

It amazes me how much I would change if I would do a 2nd edition. So much has happened since then.

Y(J)S

Is the issue symbol timing recovery or carrier tracking (derotating). 

For fully digital implementation of Rx front end there are four distinct issues:

1) carrier tracking:

a) derotating by removing carrier residue frequency

b) locking phase in doing above

3) symbol timing recovery

a) tracking symbol rate

b) locking to symbol phase (peaks and dips)

Tim,

I'm not sure if it is appropriate, but you could do a search on "Time to Digital Converter" (TDC).

regards,

Neil

Hi Tim,

   Here is one paper which can help you.

Simultaneous clock phase and frequency offset estimation,

K.E. Scott ; E.B. Olasz

IEEE Trans on Comms. 1995

   The main concept is the emergence of a symbol rate sinusoid in a squared PAM signal stream. Squaring operation, however, drowns the frequency offset information. So delay and multiplication which you're talking about is based on a similar principle but for both clock phase and frequency offset estimation, for which the paper is a good reference.