### andrew stanford-jason (@andrewstanfordjason)

Thank you both, in my specific situation I have hardware that can "multiply" and accumulate 256 one bit values by 16 bit values producing a single multi bit output....

Thanks a lot, I'll go through your paper. In reality I won't be performing any multiplies in the first stage but I tried to simplify my question as it was getting...

I would like to design an FIR filter to decimate a high rate 1 bit signal to a low rate high bit signal. Due to implementation constraints I have fixed filter length...

I have written a PDM to PCM library in software. The relevant documentation is:https://www.xmos.ai/download/lib_mic_array-[usergu.... It documents the filters used...

I would use a cascade of FIR filters. I implemented a microphone PDM to PCM converter in software as three cascaded FIR filters with a divide by 8, divide by 8...

There are many ways to deal with this but one would be to have the butterfly operator include an optional pre-left-shift. Each butterfly would also update a register...

You cannot shift any single butterfly left you need to do the whole stage, for this reason you might want to allocate yourself a bit of headroom and if at the end...

Are you asking if n starts at zero? If so then yes. I would typically define negative x(i) = 0 (i.e. initialise x(0) to be zero)

I typically do this the other way around, i.e.x(n) = [x(n) x(n-1) ... x(n-L+1)]^Te(n) = d(n) - x(n)*w(n)w(n+1) = w(n) + mu * x(n)^T * e(n)Then there is no need...

during this change of frequency of 1700.0Hz to 1700.5Hz what happens to the rest of the spectrum? i.e. should the 500Hz and 2500Hz remain unchanged?

Are you doing time or frequency domain block processing? Frequency domain is much faster for long FIR lengths. Also depending on how much latency you can afford...

I have implemented an echo canceller and my recommendations are:Linear algebraFrequency domain implementation of convolutions and correlationsFrequency domain adaptive...

To be clear you want to shorten a 1024 tap FIR down to 3 taps whilst preserving the magnitude response but are willing to compromise on the phase response? Will...

Results time, I went with a polynomial approximation. For those interested exp.ctwo_to_the_power.pyThese are the python I used to generate the coefficients and...

I have a need to raise two to the power of a fixed point number, for example 2**(Q31(-0.4)). Does anyone know an efficient way this I can implement this to a reasonable...

I'm sure this would work but if you are trying to detect tones then this sort of solution is like using an n squared algorithm to solve a problem that can be solved...

By far the easiest way to reduce the sidelines of a delay-sum beam former for a linear array is to implement array shading, essentially to weight each sensor a...

Apologies for the poor description, I've now looked further into what is happening. My observations are that if I use uncorrelated broadband noise as my input for...

I have implemented an adaptive filter using an LMS based approach. The purpose of the filter is to subtract a signal X from a signal Y where Y is assumed to have...

I see from:https://www.dsprelated.com/freebooks/sasp/Overlap_...That:The Bartlett window is clearly COLA for a wide variety of hop sizes, such as , , and...

I am doing some block based adaptive filtering and need to reconstruct the signal after filtering. I would like to parameterise the hop length(step size) between...

Given the unrestricted definition of this problem I would like to park in the arts and crafts store giving both AB

I wrote a quick and dirty numerical test, cic python, i get:Decimation ratio: 2 SNR: 7.65218361275dBDecimation ratio: 3 SNR: 4.10244607988dBDecimation ratio: 4...

Hello, I am playing with noise suppression for voice processing applications. I have done a bit of reading and thought it sensible to ask if anyone could advise...

I'm using an xcore processor. On which divides can be about 10 times the cost of a multiply from a LUT.

That's a nice idea. I'll model the error and see how much interpolation i can get away with as a massive LUT is not preferable but the speed it offers is. I assume...

I am doing some spectral subtraction type DSP and I have found that one of the major sources of computation is the adjustment(via subtraction) of the complex frame...

I have done work on high speed PMSM motor control. For motors with high number of poles rotating at high speeds the control loops benefit from very high rates. I...

Thanks, I like the idea of the optional increased test coverage.This particular device is able to produce it's own sound(with an attached speaker). Maybe using that...

The purpose of a 10-30 seconds test limit is to facilitate testing a lot of PCBs in a short amount of time, as time costs money. Ideally, the microphone testing...

Hello, I am writing some manufacture tests for digital microphones (an array of) attached to a PCB. I want to verify that they are 1) producing valid audio without...

Hello, I have implemented an adaptive blocking matrix(ABM) as part of a robust generalised sidelobe canceller. This involves using LMS to cancel the output of a...

To further explain what I am trying to achieve: I am implementing a polyphase decimation FIR, say divide by 8, with a 16x16 multiply accumulate to a 32 bit accumulator...

Agreed, I will do some reading so that I can better describe what I am trying to define. My feeling is that I would like to be able to know that a signal from 0 dBFS...

The filter is a polyphase symmetric FIR with varying coefficient quantisation, i.e. each coefficient has 14~16 bits of information(mantissa?). In effect the coefficients...

This is defiantly a linear with insignificant aliasing. I was thinking that dynamic range was: "the ratio of the largest to the smallest intensity of sound that...

I have a filter that I am unable to analyse analytically to derive its dynamic range so I would like to analyse it by observing it. The filter performs a decimation...

As you might be able to tell, due to the speed, I am sort of limited to the dropping and summing of samples(and other simple operations).

I have run three simulations. In all simulations I ran a 5th order PDM modulator with a 1kHz input signal and a 1 bit 3.072MHz output. I then took the FFT(hanging...

Thank you very much for all the ideas, I'm going to run some simulations and come back with my results.

Certainly, the system in which I am working is receiving a 16kHz clock from an external source. The chip I am programming can generate clocks very close to 16kHz*192...

Thanks, both of you. I thought I would have to go to the lengths of a proper asynchronous sample rate converter with which I am familiar. What I was curious too...

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