The significance of Upsampling at QPSK transmitter ?

Started by moaado in comp.dsp7 hours ago 2 replies

Hello, I would like to ask why would we need the upsampling process for bits in Transmitter side? We do upsample then pass it through matched...

Hello, I would like to ask why would we need the upsampling process for bits in Transmitter side? We do upsample then pass it through matched filter then modulate it, but why and how to choose the upsampling factor ? To be more precise, what would happen if we pass the bits through the matched filter without upsampling? This is in QPSK transmitter and can be generalized for all other digi...


Need Help

Started by Anonymous in comp.dsp1 day ago 3 replies

Can anybody provide me the solution for following problem. It will be great help. Adaptive filter with variable update equation: Develop...

Can anybody provide me the solution for following problem. It will be great help. Adaptive filter with variable update equation: Develop a stochastic gradient adap-tive filter that attempts to minimize the following cost function: J(n)=E{|e^2(n)|}. e(n) =1 Discuss the possible advantages and disadvantages of your algorith


Low-overhead high quality sine wave generation

Started by Piotr Wyderski in comp.dsp2 days ago 18 replies

Resonant filters are often used for this purpose, but with a remark that they need some way of amplitude control, because the numeric errors can...

Resonant filters are often used for this purpose, but with a remark that they need some way of amplitude control, because the numeric errors can make it rise without control (gain > 1) or decay to 0 (gain < 1). I don't know about you, but for me it was a great surprise to discover that for certain "magic" values of amplitude the error integrated over the entire period is *exactly* 0, which


Good phase detectors for low-frequency software PLLs

Started by Piotr Wyderski in comp.dsp3 weeks ago 4 replies

I am simulating a software PLL intended to lock to mains, which here is 50Hz. The problem is, as usual, in selecting a good phase detector. For...

I am simulating a software PLL intended to lock to mains, which here is 50Hz. The problem is, as usual, in selecting a good phase detector. For high frequency application the JK/D edge-sensitive digital phase detectors work very well, but for 50Hz the number of edges per second is low, hence the covergence is slow (or with significant ringing). OTOH, the basic multiplying detector is real-ti...


Precise and repeatable delay generation

Started by Anonymous in comp.dsp4 weeks ago 10 replies

Hi all, I am faced with the following problem. I need to generate 1MHz square wave where the phase delay has to be controlled precisely and...

Hi all, I am faced with the following problem. I need to generate 1MHz square wave where the phase delay has to be controlled precisely and repeatedly. The duty cycle of this signal can be anywhere between 40%-60%. The delay should be able to be incremented in approx. 10ps steps and the resulting 1MHz square wave jitter needs to be around 100fs or better. I was thinking about usin


machine learning vs interpolation

Started by Cagdas Ozgenc in comp.dsp1 month ago 18 replies

Greetings. I have been using neural networks and other machine learning tools for sometime time. Yesterday the following question popped up in...

Greetings. I have been using neural networks and other machine learning tools for sometime time. Yesterday the following question popped up in my mind however: Why do we use machine learning tools when we could achive similar results with plain interpolation? Let's assume a noise free regression scenario (not classification and no measurement errors). In the case of infinite samples and...


DSM integrator - how many bits?

Started by Piotr Wyderski in comp.dsp1 month ago 2 replies

I'd like to implement a first-order delta-sigma power amplifier in Verilog. The input stream is N=16-bit wide (signed). How many bits should the...

I'd like to implement a first-order delta-sigma power amplifier in Verilog. The input stream is N=16-bit wide (signed). How many bits should the integrator have? Common sense says it would be enough for the worst-case delta (=N+1) + the actual content (also N+1), so N+2 bits. Is it correct? Can it be done with just N? Best regards, Piotr


Low memory footprint decimation

Started by Piotr Wyderski in comp.dsp1 month ago

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are...

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are 8 channels of 12 bits@100kHz each and a single digital quadrature mixer running at 310kHz, also 12 bits. The hardware is an 80MHz ARM CortexM3 equipped with a coprocessor called DFB, running at the same speed, with single-cycle 24x24-> 48-bit MAC an


Finding maximum of sinc in 0..1

Started by jungledmnc in comp.dsp1 month ago 11 replies

Hi folks, the audio world is sort of obsessed with sort of "true peak level". Unfortunately it is rather tricky to calculate, so it is...

Hi folks, the audio world is sort of obsessed with sort of "true peak level". Unfortunately it is rather tricky to calculate, so it is calculated by oversampling to about 192kHz and taking the normal peak level. Sadly that's really not true peak level. So how about the (nearly) correct value - if we take say 2 * N + 1 samples around each sample S[0] (hence S[-N] .. S[N]), we can calculate ...


How can a filter impulse response be interpolated?

Started by fl in comp.dsp1 month ago 19 replies

Hi, I know how to interpolate a digital signal. It is first interpolated by inserting 0's. For example, one can add 4 0's to each data for a...

Hi, I know how to interpolate a digital signal. It is first interpolated by inserting 0's. For example, one can add 4 0's to each data for a 5 times interpolation. Then, a low pass filtering to eliminate the aliasing frequency. Now, I have a low pass filter from 0 to 10 MHz pass band with a sampling rate of 40 MSPS. I want to get the same 0 to 10 MHz response (it is not a flat pass band...


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