## Forums More comp.dsp

## PID controller in a robotic sailboat

inI'm a long time lurker, here because occasionally the math is interesting. But recently, I got a chance to do some embedded programming. I...

I'm a long time lurker, here because occasionally the math is interesting. But recently, I got a chance to do some embedded programming. I thank Tim Wescott for his intro to PID controllers. I'll get to that bit, but first there's some background material. There's a program at Community Boating in Boston, Mass. which since at least 2013 has let high school students design software for con...

## Special offer

Dear All, This is a limited time (genuine) offer for a free license of FFT Properties...

Dear All, This is a limited time (genuine) offer for a free license of FFT Properties v6.1: https://www.dewresearch.com/products/fft-properties Anybody who is kind enough to submit a step by step reproducable bug report to support@dewresearch.com until Sunday 19th of November 2017 will receive a free license. Common sense applicable, no missing features etc... Wish you happy day at wo...

## FW: Discrete Fourier Transform (DFT) viewer and/or file format

Dan Hitt posted the following on the Debian user list. [https://lists.debian.org/debian-user/2017/11/msg00444.html]. I suggested he ask on...

Dan Hitt posted the following on the Debian user list. [https://lists.debian.org/debian-user/2017/11/msg00444.html]. I suggested he ask on comp.dsp . > I have some DFTs that i wish to inspect. (Apparently DFT is a common > acronym, but here i mean Discrete Fourier Transform. And properly > speaking it doesn't make sense to inspect a transform, but only to > inspect transformed data, but

## The significance of Upsampling at QPSK transmitter ?

inHello, I would like to ask why would we need the upsampling process for bits in Transmitter side? We do upsample then pass it through matched...

Hello, I would like to ask why would we need the upsampling process for bits in Transmitter side? We do upsample then pass it through matched filter then modulate it, but why and how to choose the upsampling factor ? To be more precise, what would happen if we pass the bits through the matched filter without upsampling? This is in QPSK transmitter and can be generalized for all other digi...

## Need Help

inCan anybody provide me the solution for following problem. It will be great help. Adaptive filter with variable update equation: Develop...

Can anybody provide me the solution for following problem. It will be great help. Adaptive filter with variable update equation: Develop a stochastic gradient adap-tive ï¬lter that attempts to minimize the following cost function: J(n)=E{|e^2(n)|}. e(n) =1 Discuss the possible advantages and disadvantages of your algorith

## Low-overhead high quality sine wave generation

inResonant filters are often used for this purpose, but with a remark that they need some way of amplitude control, because the numeric errors can...

Resonant filters are often used for this purpose, but with a remark that they need some way of amplitude control, because the numeric errors can make it rise without control (gain > 1) or decay to 0 (gain < 1). I don't know about you, but for me it was a great surprise to discover that for certain "magic" values of amplitude the error integrated over the entire period is *exactly* 0, which

## Good phase detectors for low-frequency software PLLs

inI am simulating a software PLL intended to lock to mains, which here is 50Hz. The problem is, as usual, in selecting a good phase detector. For...

I am simulating a software PLL intended to lock to mains, which here is 50Hz. The problem is, as usual, in selecting a good phase detector. For high frequency application the JK/D edge-sensitive digital phase detectors work very well, but for 50Hz the number of edges per second is low, hence the covergence is slow (or with significant ringing). OTOH, the basic multiplying detector is real-ti...

## Precise and repeatable delay generation

inHi all, I am faced with the following problem. I need to generate 1MHz square wave where the phase delay has to be controlled precisely and...

Hi all, I am faced with the following problem. I need to generate 1MHz square wave where the phase delay has to be controlled precisely and repeatedly. The duty cycle of this signal can be anywhere between 40%-60%. The delay should be able to be incremented in approx. 10ps steps and the resulting 1MHz square wave jitter needs to be around 100fs or better. I was thinking about usin

## DSM integrator - how many bits?

inI'd like to implement a first-order delta-sigma power amplifier in Verilog. The input stream is N=16-bit wide (signed). How many bits should the...

I'd like to implement a first-order delta-sigma power amplifier in Verilog. The input stream is N=16-bit wide (signed). How many bits should the integrator have? Common sense says it would be enough for the worst-case delta (=N+1) + the actual content (also N+1), so N+2 bits. Is it correct? Can it be done with just N? Best regards, Piotr

## Low memory footprint decimation

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are...

Hello, so I finally have some time to return to the problem of the multichannel decimation on PSOC5LP. The situation is as follows: there are 8 channels of 12 bits@100kHz each and a single digital quadrature mixer running at 310kHz, also 12 bits. The hardware is an 80MHz ARM CortexM3 equipped with a coprocessor called DFB, running at the same speed, with single-cycle 24x24-> 48-bit MAC an

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