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SDR/DSP Question

Started by OnMyOwn 2 years ago22 replieslatest reply 2 years ago249 views
I'm trying to build a simple SDR transmitter.  My plan is to use a TMS320C6713 DSK to generate and modulate a sine wave (AM and SSB, no digital) at an IF frequency (455 kHz or lower if necessary), run the digital signal from GPIO through a DAC, and then upconvert to HF (3 to 30 MHz) and amplify to 5W on the way to the antenna. So, two questions:

1.  Is this approach workable in terms of the available hardware?

2.  Is the TMS320C6713 DSK the best choice for this application?  (I've read the posts on the "#FAQ/DSP Dev Kits for Learning" forum, don't want to use the too-old ADSP-2181, and I'm confused by advice to use ARM M7 or PSoC5, since I believe these are MCUs, not DSPs).

I hope I'm posting to the right forum.  Thanks for any advice you can offer.
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Reply by chalilAugust 15, 2020


an IF of the order 455kHz would require high rate IO (with DMA) to drive the DAC. GPIO won't serve the purpose at this rate.  typically,if you'are using PCM kind of samples, you would have 8+ bits for every IF sample. 

IMO, An ARM with little bit of configurable IO to drive the IF DAC would address your requirement. like quicklogic EOS-S3 which has tiny FPGA and a cortex M4 core. Most ARM cores can handle DSP operations such as FIR/IIR/FFT/etc. CMSIS library enables one to avail all this with no/little coding.  

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Reply by OnMyOwnAugust 15, 2020

OK, thanks very much, especially for clearing up the ARM core question.  I'll look into the CMSIS library.

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Reply by napiermAugust 15, 2020

I pretty much always start at the interface to the D/A (A/D) and work backwards.  The interface works at a fixed rate so the SDR has to source and sink the data so that there is no underflow/overflow.  All the filtering up/down conversion and system design is influenced by that link.  So picking a good clock rate that is a some multiple of your data rate can make life much easier esp. if it is asynchronous comm and no rate matching (or clock recovery) is needed.

Also, if your D/A (A/D) can run fast enough to directly oversample at your desired IF then you can avoid a host of RF problems.  Much easier to spec. filters and avoid noise funneling and spurs if you can directly oversample.  The alternative is to work in one of the Nyquist images and design RF band-pass filters to select the desired signal.  No easy task.

Have fun,

Mark Napier


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Reply by OnMyOwnAugust 15, 2020

Thanks for the strategy of working back from the D/A interface -- makes sense in terms of simplifying things.  This project will be a big step up for me as someone who's always worked on the analog side til now.  

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Reply by neiroberAugust 15, 2020

Hi,

A cleaner solution would be to perform the upconversion in the digital domain.  You could use a quadrature Digital UpConverter (DUC) chip, which includes an upconverter and DAC.  For example, Analog Devices has the AD9856, which operates to 200 MHz (This chip might not be compatible with your application, though).

Unfortunately, their website is acting flaky right now, so I have not seen any details on the chip.

regards,

Neil


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Reply by napiermAugust 15, 2020

Hey Neil!

Yes, upsample and use a DDC strategy to go direct to RF.  I missed that 30MHz is your highest frequency.

Also for full disclosure, I design for FPGA/ASIC hardware solutions and haven't touched a DSP processor for 25 years now.  The data path design process is similar but there is at least an order of magnitude more processing power available.  The Artix 200 I'm using now has over 700 DSP blocks.  There's an inherent advantage in parallelism over a processor which does one thing at a time even if it does so very quickly.

Mark


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Reply by OnMyOwnAugust 16, 2020

OK, thanks for that.  I briefly looked into using an FPGA instead of a DSP, but I know almost nothing about them other than that they are programmed with VHDL or Verilog, so using them would mean an even steeper learning curve than I face already with DSPs.  But someday...

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Reply by OnMyOwnAugust 15, 2020

That would be great, assuming there is some board with the chip already mounted (I don't think I'm capable of designing the circuit from the chip datasheet alone).  Thanks for the suggestion.

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Reply by ChuckMcMAugust 15, 2020

I am going to echo everyone else's suggestion that you avoid using the TMS320C6713. Unless you are into retro hardware (which is cool in its own right, but the joy their is overcoming the lack of tools support rather than the outcome I suspect).

For working under 100 MHz it is simplest (in terms of things you have to learn and get right) to generate base band, mix it with a local oscillator to up convert to the frequency and use an off the shelf band pass filter on the output to trim spurs out of the resulting signal.

Off the shelf Cortex-M4 microprocessors from ST, NXP, Atmel, and TI can all generate the base band easily with a typically DMA driven 1 MSPS 10 - 12 bit DAC. An off the shelf frequency generator like the Si5351 can give you a very stable reference frequency, and an out the box mixer from mini-circuits and band pass filter can insure that any mixing artifacts don't make it into the output signal. 

I bread boarded a system for a class like this based on an RFExplorer Up Converter, an STM32F429 Discovery board, and mini-circuits band pass filter, and a single transistor class A linear amplifier which produced about 100 mW of output. I used these parts because I had all of them on hand, bought new it would be about $200 worth of gear. But you can buy mixers and NCO boards on ebay for a few bucks and could likely do it for less than $30 without too much trouble (not get to 5W but to get to a few 100 mW).

That said, once you've got that under your belt, if you want to take the next step then you really need an FPGA and one of the Analog devices DACs (like AD9364). AD has a simple SDR called the ADLM-PLUTO which they used to sell for $99 which included schematics and could teach you a LOT about SDRs and how they work. It can both transmit and receive and the simplest way to use it sometimes is to have it transmit to itself so that you can build both sides of the pipeline (transmit and receive). It uses the Zynq 7010 chip which is both an ARM CPU and an FPGA fabric. 

If you want to step your game up further, then you can combine an Ultra96 board (which has an Ultrascale Zyng) with a LimeSDR-A module (which is the 'Radio' part) and build anything from a dual band 2M base station to a 4G LTE cell tower.

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Reply by OnMyOwnAugust 16, 2020

OK, so definitely NOT the TMS320C6713!  And the consensus seems to be to start with baseband.  I've built a couple of DDS VFOs based on Si5351 and AD9850 so I'd hav e a reference frequency available.  I considered the Pluto a couple years ago when I first looked into SDR, but decided against it because it seemed like a black box to me; I didn't know schematics were available, so I might take another look now.  Thanks for the great suggestions.

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Reply by jbrowerAugust 15, 2020

OnMyOwn-

Definitely you can't use DSK C6713 for a new project if for no other reason that it's circa 2003 and you would find it very hard to get support. These days, if you can't go online at 2:00a and ask a question and have an answer by 4:00a, then you've got the wrong approach, don't do it.

The answers you got here so far for target hardware are excellent. My additional comment is that you can simulate with non-real-time C coding on an x86 or ARM Linux server using gcc build tools. This is a fast way to get started, and gives you time to think about which SoC and/or dev board to use. When the time comes to port, if you have all C code you won't face any major issues, and you will be in an excellent debug situation, being able to port block by block against a known-good reference.

If you take the simulation route, spend time thinking about I/O. The typical D/A setup accepts buffers at regular intervals, so your code should be doing something very similar, maybe writing to a wav file at intervals timed by a Linux timer callback function or similar, with the buffer size configurable.  Wav files can have any Fs, 2-4 bytes per sample, and provide a flexible way to interface to analysis tools such as MATLAB, Audacity, Hypersignal, etc.

-Jeff

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Reply by OnMyOwnAugust 16, 2020

Very interesting.  I haven't been thinking of simulation because of the obstacles to doing real-time programming in a multitasking environment.  But I've written working C code for filters and synthesizers, so putting blocks together in a linux server before moving to hardware wouldn't be too difficult (er, famous last words).  Anyway, thanks!

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Reply by Braddon Van SlykeAugust 15, 2020

Here's another data point for you to consider - I did something similar two years ago, where I used an LTC5598 baseband modulator, along with a Si5338 clock generator, to modulate IQ signals from 5 to 1200 MHz:

http://www.arrl.org/files/file/QEX_Next_Issue/MarchApril2019/VanSlyke.pdf

For the I and Q generation, I used a TMS320F28377S, which contains 3 DACs, so I didn't have to add extra DAC hwd, but I did have to add post-dac filtering.  The downside with that dsa is, it's got everything and the kitchen sink, thus the learning curve was steep.

I also tried generating signals in Octave, saving the IQ data as L/R into a wav file, then playing out using an external usb sound adapter.  Of course, your sample rate is limited to audio frequencies, but if you're transmitting on HF, your signal probably shouldn't be any wider than 3 kHz.  One sound adaptor I used, which I normally use for music, worked fine.  Another adaptor I used, a cheapo one for $3 on ebay, did not faithfully reproduce the phase properly and the IQ were not 90% separated.  

With these modulator chips, you'll also need output filtering, as I think you'll have 3rd and 5th order harmonics, and you want to remain FCC compliant.  I'm assuming you have some sort of licence, e.g. amateur, if you're going to actually broadcast, and not just dump into a dummy load or push into a terminated cable.

Regarding amplification, I think those modulator chips output about a milliwatt at full input.  For a two-meter transmitter, I used a SPF5043Z as a preamp to get me to about 20 mW.  I can't remember offhand the p/n of the amp I used after that to get me to about 5w.  Again, that was for 2m, so you'll need some different amplification for HF frequencies.   


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Reply by OnMyOwnAugust 16, 2020

Thanks, and my compliments on a well-written article.  I'm not sure I want to get into that much construction at this point, but the article does help me understand baseband modulation better.  I've built a nice little 5W PA, so once I get something which can put out 100 mW or so, I'm all set (WB2OSR, although I'm never on the air).

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Reply by cpeckhamAugust 15, 2020

Actually the easiest method is to go straight from baseband I and Q signals to RF. Take a look at the EDENDSP group on gwoups.io. The file section has a complete transciver using the Microchp DSPIc33ch part. Works great I am using it for Ham radio work now. Also it has a multirate sytem that allows baseband for SSB and 8Khz IF for AM.

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Reply by OnMyOwnAugust 16, 2020

Thanks, I've never come across that group before, and that Eden DSP is a nice looking radio.

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Reply by cpeckhamAugust 15, 2020

BTW: I should add using the EDENDSP approach requires about $50 for the development board. Inexpensive solution.

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Reply by OnMyOwnAugust 16, 2020

OK, thanks again.  Very reasonable price.

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Reply by Tim WescottAugust 15, 2020

There are just so many ways that you can do this that you're spoiled for choices.  In addition to the other suggestions, I have these:

  • See if you can find a digital output board (or USB audio thingie) for your PC and just use it to generate the signal.  This could even be a sound card, using the left and right channels to generate I & Q for direct upconversion (and left & right audio in for the receiver, if you wanted to).  Then if you want a self-contained unit later, marry a digital part to your already-debugged analog part.  This will require some fighting with the PC to make it real time, but you already have the hardware!
  • You have wide lattitude in your conversion scheme.  
    • You can go with a 0Hz IF.  This means generating I & Q channels and upconverting.  You'd need to live with the spurious carrier (there will be one), but you can use audio DACs.
    • Go with a low IF -- maybe 50kHz -- then mix it up to 455kHz, and then up to your transmit frequency.  This involves a fairly long superhet transmitter, with all the opportunities for spurs that implies.  It means you need a DAC (and processor) that can handle 200ksps or so.
    • Generate the signal directly with a low-ish speed DAC, and use the alias around 455kHz.  This is almost the above solution, but doesn't involve a separate mixer from the first IF to 455kHz (or it involves a "mixer" operating at your sampling rate).  For example, if you use a 200ksps DAC and generate a signal centered around 55kHz, you'll get signals at 55kHz, 145kHz, 255kHz, 345kHz, 455kHz (yay!), 535kHz, etc.  That's enough spacing that it should be easy to select for 455kHz.
      • Do the above, but chop the DAC output.  Playing around with this, it seems like chopping it to pulses 1.5us wide will give a pretty good peak at 455kHz and pretty good attenuation at 345kHz and 545kHz, but you'll want to play with the exact width to get the best peak to attenuation ratio.
    • Generate the signal with a high-speed DAC and low-pass filter -- either around 2Msps if you want filter down to a 455kHz IF, or a good bit above 60Msps if you want to filter down to 30MHz.  Both of these solutions probably have some FPGA resources involved.
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Reply by chalilAugust 16, 2020

If you're planning IF <200kHz, simplest, imo, will be to go with one of the SigmaDSP from ADI, such as ADAU170x. 

merits :

  • no programming required
  • rich DSP library, including different types synthesizers, filters, eq, limiters,etc. 
  • in build DACs upto 192kHz 
  • in built PLL, high SNR, etc support for external clock

demerits:

  • no programming support or closed programming. you have to manage with supplied DSP / Ctrl blocks.
  • when the schematic complexity increases effective CPU load available for a give system reduces non-proportionality. This is due to the fact that higher level algorithms are required to be implemented with low level DSP blocks which are less efficient than direct implementation of the algorithm, for example,  if one want to implement a AM-SSB several DSP blocks are required to be used which adds overheads when compared to directly implementing a DSP module to handle SSB. good news is that there are higher level chips available in the same family. you can migrate one solution to another with almost zero effort.  

I hope, one can do AM or FM at 192k with ADAU17xx.    

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Reply by OnMyOwnAugust 16, 2020

Thanks, that's an impressive chip.  I see that AD has an evaluation board for $195, which I might try for this application.  As you can see, I now have many alternatives to consider!

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Reply by OnMyOwnAugust 16, 2020

Wow, thanks for all those suggestions!  I thought I'd be starting on this project this week, but with all these new ideas I'll have to take at least another month to consider new approaches.  Thanks again.